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Consider a cache memory which is 30 times faster than main memory and it can be used 90% of the time. Speed up gained by the cache memory is ____.
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I am getting 7.5
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Your final calculation must have been 1/0.133, right? Mine too. Answer came out as 7.51. But they didn't consider cache hit time when it didn't hit cache and went to memory to look. So they did 1/(0.03 + 0.1) and gave the answer as 7.69-7.70. I wonder whether the approach is correct or not.
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I am also getting 7.5.

I think by default we consider hierarchical arrangement.
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No ...i did by assumption.

Let memory time be 300 sec.

then time taken by cache = 10 sec

$speed\ up = \frac{memory}{memory\ with\ cache} = \frac{300}{0.9*10+0.1*300} = \frac{300}{39} = 7.69$

Here they have given that 90% of time we use cache so 10% time we use only memory. We will not use heirarchial access formula here.

if we will use mem+cahe in 10% case also then that statement will become wrong.

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This question is equivalent to asking:

Consider a program in which 90 % of the of the part can be sped up and the speed up is 30 times. What is the overall speedup?

Simple application of Amdahl's law, the answer should be $\frac{1}{0.1 + \frac{0.9}{30}}$

However, if you want to see it as using the memory itself, let $t_a$ be the time to access the main memory, and let $t_b$ be the time used to access the cache.

Then, $$\text{Speedup} = \frac{t_a}{h  \cdot t_b + (1-h) \cdot t_a}$$

Here, $\frac{t_a}{t_b} = 30$, so we essentiallly get the same result.
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@Satbir - They haven't mentioned anything about whether it is hierarchical or not. Look at Bikram Sir's comments in this and he says by default we must consider hierarchical as @tp21 mentioned as that is the real world scenario: https://gateoverflow.in/130206/co-hierarchical-vs-simultaneous-memory-organization

 

@goxul - What you said would be correct if the question was framed as you said but I think there is a difference when it comes to memory access vs simply saying a program is sped by 30 times. Amdahl's law is for parallel computing, whereas I can argue that this question shouldn't be considered parallel at all since by default we are to consider hierarchical organisation.

 

If I am wrong somewhere, please let me know. And thanks for contributing guys. It is much appreciated.

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@tamaldeepmaity You can ignore the part where I said use Amdahl's law. I've mentioned an alternate derivation for the same, using the data given in the question, which gives the same result. 

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Actually here the question is not related to hierarchial or sequential access. They have just given 2 independent memories and how we are using them.
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Hamacher book. They considered miss penalty to include the cache access time. I am really confused. If you just put numbers in formula I suppose we can get 7.5. But it doesn't sound logical. Why would they consider two separate memories and then name them 'Main memory' and 'cache'?

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Yes you are right. I also followed that concept only at first. They have not framed the question properly.
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What definition of miss penalty you are following--

1)Extra time required to load block from main memory to cache when miss occurs.

One which Arjun Sir followed in below question-

(https://gateoverflow.in/118371/gate2017-2-29)

OR

2)Time required to access data when miss occurs.(This is given in Hamacher)

 

Confusion is do we consider cache access time in miss penalty itself?

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