In a two-level cache system, the access times of L1 and L2 are 4, 15 clock cycles respectively. The miss penalty from the L2 cache to main memory is 30 clock cycles. The miss rate of L1 cache is thrice that of L2. The average memory access time(AMAT) of this cache system is 6 cycles. The miss rates of L1 and L2 respectively are:
i am really confused as to which time is to be considered while solving such questions.
also, the explanation mentioned in the test series is very complicated and lengthy,is there any approach to solve it in a fast manner and get the concept in place right.