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The virtual address generated by a CPU is 32 bits. The Translation Look-aside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4- cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is

(A) 12 bits

(B) 15 bits

(C) 16 bits

(D) 20 bits
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@shashin

as you have mentioned earlier that the number of bits required to represent TLB depends on the number of entries.

So here shouldn't the TLB tag be of size $6bits$ as we have $64$ $entries?$

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You're forgetting the fact that TLB is pretty much a cache, and set associativity applies here too.

Number of sets $= \frac{number of lines}{associativity} = \frac{64}{4} = 16 \implies 4$ bits to represent a set.
Now think of the TLB tag if there was no set associativity concept.

TLB tag bits = page indexing bits

i.e. no of TLB tag bits $= VAS - page\:offset = 32-12 = 20$ bits

Now 20 bits to address a TLB entry. Of these, 4 bits are taken to identify a set. What remains is the tag bits.

i.e. $20 - 4 = 16$ bits for the tag.

There is absolutely no need to get confused. Whatever rules and logic apply for a cache, apply for the TLB too. Including the concept of associativity and tags.
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number of bits required to represent TLB depends on the number of entries

This is true in case of a direct-mapped TLB, exactly the same as a direct-mapped cache. If associativity is mentioned, you need to consider that, exactly like you would for a set-associative cache.

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@shashin

Can you help me understand segmented paging and how to solve sums on it?

Do you have any resources for that?

+1 vote

since TLB is also like a cache memory, so the same concept can be applied here.

Virtual address is 32 bits and page size is 4KB i.e 12 bits.

so, 32 - 12 = 20 bits remaining for tag and number of sets.

Question says TLB has 64 entries , Number of sets  = Number of entries/associativity

= 64/4 = 16.

so 4 bits for cache sets.

Therefore number of bits in tag field = 32-(12+4) = 16bits.

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