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A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4-way set associative LRU cache is used is ________. (Upto 1 decimal places)
100, 104, 108, 104, 107, 108, 105, 102, 108, 103
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