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A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache is increased from one word to four words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____
(Upto 2 decimal places)
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$\text{Assuming 1 cycle is required to read word from cache memory without miss}$

$\underline{\text{Under 14.8% miss rate}}$

$\text{Miss from cache to main memory to send an address }\rightarrow \text{ 1 cycle}$

$\text{Read a 64 bit word from main memory to cache } \rightarrow \text{ 8 cycles}$

$T_{avgRead } = 14.8 \times (1 + 8) + 85.2 \times 1 = 218.4$

$\underline{\text{Under 2.6% miss rate when cache line size is increased}}$

$\text{Miss from cache to main memory to send an address }\rightarrow \text{ 1 cycle}$

$\text{Read 4 words each of 64 bit from main memory to cache } \rightarrow 4 \times 8 = \text{32 cycles}$

$T'_{avgRead } = 2.68 \times (1 + 32) + 97.4 \times 1 = 183.2$

$\text{SpeedUp} =\dfrac{T_{avgRead }}{T'_{avgRead }} = \dfrac{218.4 \text{ cycles}}{183.2 \text{ cycles}}$

$\text{SpeedUp}=1.192$
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