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Consider a RISC processor with an ideal CPI, where 25% of the total instructions are load and store instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles and cache miss rate is 2%. Which of the following are correct? (MSQ)

A The effective Cycle Per Instruction (CPI) for the system with the cache is 3.5 CPI. 

B The effective CPI for the system with the cache is 5 CPI. 

C CPI for handling cache misses is 2.9. 

D CPI for the handling cache hits is 2.45. 


How to solve this, unable to get any option...

ago in CO & Architecture by (23 points) | 37 views

Option (A)


As it is a RISC processor the ideal CPI = 1.

Now, number of memory access per cycle = 1 (instruction fetch) + 0.25 (load or store instruction) = 1.25

Stalls per memory access = 0.02 * 100 = 2

Average stall per instruction =   number of memory access per cycle * Stalls per memory access = 1.25 * 2 = 2.5

Effective CPI = Ideal + average stall per instruction = 1 + 2.5 = 3.5 CPI

Actually it is a MSQ, answer given by ME is B,D
No solution given?

Actually answer is there, but I could not understand it.

Post the answer bro
checked the edited comment above
@Abhineet Singh that should be 102 instead of 1.02 I guess, thanks for the nice question.

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