Consider a RISC processor with an ideal CPI, where 25% of the total instructions are load and store instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles and cache miss rate is 2%. Which of the following are correct? (MSQ)
A The effective Cycle Per Instruction (CPI) for the system with the cache is 3.5 CPI.
B The effective CPI for the system with the cache is 5 CPI.
C CPI for handling cache misses is 2.9.
D CPI for the handling cache hits is 2.45.
How to solve this, unable to get any option...