Tga test series

Question

 

Answer 1

The preset input of D flip-flop is set to 1 so, regardless of input the output Q1 will be 1 (It would be 1 regardless even if preset was 0).

As Q1 is always 1 and Q1’ is always 0, the output of the OR gate will be (0 + 1) = 1.

The output clock from the XNOR gate will be the same clock applied to D flipflop as $A\bigodot 1 = A$.

The JK flip flop has both its input set to 1, so it will act as a T flip flop and will toggle with every positive edge of the clock. The T flip flop will toggle it’s output when Q2 goes from 1 to 0 (negative edge triggered), the counting sequence will be $$Q_3Q_2Q_1\\001\\011\\101\\111\\001$$

So output of counter are always odd numbers, and mod of the counter is 4.

Option A & Option C