in CO & Architecture
30 views
0 votes
0 votes

Question: 

Consider the code sequence shown below running on the basic 5-stage instruction pipeline. Each stage takes 1 cycle without hazards. The pipeline stalls on data dependencies that cannot be fully resolved by forwarding. Load instructions do not have delay slots, therefore the value loaded into rd is used for all subsequent instructions.

Idr r2, [r6,#4]

add r4, r3, r2

str r4, [r7,#8]

add r6, r6, #4

add r7, r7, #4

add r1, r1, #-1

make a pipeline table to find number of cycle it take to complete

 

ANSWER: 

Can you please guide me with the below solution, where it goes wrong.

 

in CO & Architecture
by
71 points
30 views

Please log in or register to answer this question.

Ask
Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
Welcome to GATE CSE Doubts, where you can ask questions and receive answers from other members of the community.