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Consider a two-level memory hierarchy with separate instruction and data caches in level 1, and main memory in level 2. The clock cycle time in 1 ns. The miss penalty is 20 clock cycles for both read and write. 2% of the instructions are not found in I-cache, and 10% of data references not found in D-cache. 25% of the total memory accesses are for data, and cache access time (including hit detection) is 1 clock cycle. The average access time of the memory hierarchy will be …………. nanoseconds.

Can anyone plz provide the solution.
in CO & Architecture by (135 points) | 26 views

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25%  of the total memory accesses are for data ==> 75%  of the total memory accesses are for Instructions.

By default we use " Sequential Memory Access "


Memory Access = ( Access for Instructions ) + ( Access for Data )

Avg. Memory Access =  (% Memory access of Instructions)(Access for Instructions) + (Access for Data)(% Memory access of Data)

Access for Instructions = Cache time + Miss ratio * Penalty = 1 + 0.02*20 = 1+0.4 = 1.4

Access for Data = Cache time + Miss ratio * Penalty = 1 + 0.1*20 = 1+2 = 3

Avg. Memory Access = 0.75*1.4 + 0.25 * 3 = 1.8
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https://gateoverflow.in/118371/gate2017-2-29

@Shaik Masthan

Chk this ques.

 

AMAT=L1 access time
+L1 miss rate×L2 access time
+L1 miss rate×L2 miss rate×Main memory access time
 

Chk only the red part. Why two level miss are taken? Can we not do like this?

 

AMAT=L1 access time
+L1 miss rate×L2 access time
+L2 miss rate×Main memory access time
 

0
After L1 miss only... You have to check in L2

...

So, it should be L1 miss rate * L2 miss rate * MM time
0
Shaik once check my answer below.What is wrong in the answer below.


If there are total 100 instructions then all of them will be accessed from the instruction cache first, but only 25 of them need data access.

So, average access time =  (100( 1 + 0.02 x 20) + 25 ( 1 + 0.10 x 20))/100  = 2.15 ns
0

25% of the total memory accesses are for data

So, you have to divide by 125 but not with 100

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