Recent questions and answers in CO & Architecture - GATE CSE Doubts

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What is the difference between computer architecture and computer organization? Help me with good examples.

answered 13 hours ago in CO & Architecture by Abhinav993 (173 points) | 10 views

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What is the difference between Computer organization and Computer Architecture?

asked 2 days ago in CO & Architecture by commenter commenter (126 points) | 4 views

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Gate overflow doubt made easy cache stalls
Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory is 100 cycles.The hit time of L2 cache is 20 cycle.The ... cache is 10 cycles. If there are 2.5 memory references per instruction.How many average stall cycles per instructions are there? [closed]

asked 2 days ago in CO & Architecture by Ram Swaroop (171 points) | 5 views

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self doubt-relative addressing mode
Can anyone tell me what is the format of relative addressing mode instructions in 8086 microprocessor?

asked 3 days ago in CO & Architecture by Doraemon (139 points) | 4 views

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self doubt-gate question on addressing mode
https://gateoverflow.in/444/gate2008-33-isro2009-80#11387 consider option C. The amount of increment depends on the size of the data item accessed . register R1 suppose 300 is stored Now suppose the data is byte addressable and we want to ... ? will the R1 be incremented by 4Bytes even though it is byte addressable? I am not getting it.Please clarify. [closed]

asked 4 days ago in CO & Architecture by Doraemon (139 points) | 4 views

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differentiate between stack and accumulator based cpu organization

asked 4 days ago in CO & Architecture by yajas (102 points) | 1 view

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self doubt -addressing mode
suppose we consider register indirect addressing mode is used in a system. Now in this mode the address of the operand is stored in the register R1. It has been told that the size of the register R1 is 8 bits.then . then the maximum size of the main ... am having a confusion.(Do we used unsigned int or 2's complement number)? In C language we do used unsigned int right?

asked 4 days ago in CO & Architecture by Doraemon (139 points) | 3 views

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Self doubt on Opcode and Encoding
Can somebody give some idea, how bit-byte conversion happens in encoding?? I mean , if there are $8$ registers, we just need $3$ bit to address it. Now suppose there are $3B$ instructions , we take 24 bit to represent it. Now suppose we take ... with 15 bits $2^{15}$ what is opcodes? Why it represent in exponential format?? How it do the process of encoding??

answered 4 days ago in CO & Architecture by Debargha Bhattacharj (1.3k points) | 32 views

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Summary of hardware implementation of direct, n-way set associative and full associative mappings?

asked Aug 15 in CO & Architecture by commenter commenter (126 points) | 3 views

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Vani Qs Bank: COA
Consider the following program segment for a cpu having 3 register R1, R2, R3 Consider the memory is byte addressable with word size 16bits and the program has been loaded starting from memory location 300. If an interrupt occurs while the ADD instruction getting executed by the CPU, then the return address saved on to the stack will be _______________ (NAT)

asked Aug 14 in CO & Architecture by Hirak (1.3k points) | 5 views

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Gateoverflow question- machine instruction
https://gateoverflow.in/291233/calculate-number-of-times-zero-flag-is-reset Can someone explain to me the entire approach and ultimately the final answer ?

asked Aug 13 in CO & Architecture by user2525 (1.6k points) | 10 views

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Made Easy Hand Written Notes- Computer Organization- Machine Instructions & Addressing Modes

asked Aug 9 in CO & Architecture by dileepbhagat2196 (102 points) | 6 views

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self doubt-cache memory
Suppose a system has L1,L2,L3 Cache and M as the main memory .now suppose a word W is being searched. the CPU first searches L1 cache whose access time/latency is 10ns .Does not find it. then the CPU again searches L2 cache whose access time is ... word is brought from the main memory to the CPU .is the block containing the word moved simultaneously to the L1,L2,L3 cache?

answered Aug 9 in CO & Architecture by Hirak (1.3k points) | 9 views

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Self Doubt - Cache Memory Mapping
Any Good resource to understand Hardware Implementation of various Cache Memory Mapping techniques (Direct, Fully Associative and K-way Set Associative). I mean how many Comparators, Multiplexers, etc. are required? How do they work?

asked Aug 5 in CO & Architecture by ayushsomani (115 points) | 2 views

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computer architecture addressing modes
Implicit mode means the operand is implied and we don’t mention it in instruction explicitly.<we have 0/1 address instructions. whereas in immediate mode ,the operand is mentioned explicitly. Consider below cases and please help me identifying : PUSH 3 LD 7 PUSH A

asked Aug 4 in CO & Architecture by manisha11 (110 points) | 2 views

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Self Doubt: CO and Architecture
How many memory accesses required by the following instructions? DIV r1, r2, @(r4) Suppose instruction is one word long, as well as every address. (A) 1 (B) 2 (C) 4 (D) 6

asked Aug 3 in CO & Architecture by Hirak (1.3k points) | 6 views

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How can AR work as a source and destination at same time?

answered Aug 3 in CO & Architecture by Vimal Patel (112 points) | 39 views

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Self doubt pipeline
What is meant by tp ( cycle time) in the pipeline ?

answered Aug 3 in CO & Architecture by Abhinav993 (173 points) | 6 views

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Bypassing-Hazards
Can anyone give an example like why Bypassing cant handle all RAW hazard

asked Jul 31 in CO & Architecture by Shivateja MST (127 points) | 1 view

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CONTROL UNIT DESIGN

answered Jul 30 in CO & Architecture by Arnabh Gangwar (183 points) | 15 views

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Function Call, ISR Self Doubt
What is the difference between a function call and interrupt? and what is the difference in their micro operations?

asked Jul 30 in CO & Architecture by aditi19 (134 points) | 2 views

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OPERAND FORWARDING
Load R2, (R3) Subtract R9, R2, #30 Why operand forwarding cannot be done in the above case?

answered Jul 30 in CO & Architecture by Arnabh Gangwar (183 points) | 11 views

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CACHE-RELATED-DOUBT
When no information regarding cache is given ..and it is only told a multilevel cache then what should we consider? Hirerchial cache or Simultaneous cache?

asked Jul 28 in CO & Architecture by Ritabrata Dey (242 points) | 6 views

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PIPELINING QUESTION

answered Jul 28 in CO & Architecture by Verma Ashish (305 points) | 5 views

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PIPELINE HAZARDS
The following assembly code to be executed in a 3 stage pipelined processor with hazards and resolution. What are possible number of RAW , WAW , WAR hazards ? R0 ← (R0) + 1 Acc ← (ACC) * (R0) R1 ← (ACC) Acc ← (ACC) + (R0) M ← (ACC)

asked Jul 27 in CO & Architecture by Ritabrata Dey (242 points) | 3 views

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Addressing modes
Consider a hypothetical processor which supports both 1 and 0 instructions. A 24 bit instruction is placed in 1024 word memory. What is the range of one address instructions and zero address instructions? If there exist n-1 address instruction then how many zero address instructions are formulated?

asked Jul 26 in CO & Architecture by Kavyachinnu (102 points) | 2 views

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MICROPROGRAMING
A vertical microprogrammed control unit supports 256 instructions. The system is using 8 flag conditions and contains 48 control signals. Each instruction on an average requires 1 micro operation. What is the approximate size of control memory in bytes?

answered Jul 26 in CO & Architecture by user2525 (1.6k points) | 7 views

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Self doubt Control memory https://gateoverflow.in/181815/control-memory

answered Jul 26 in CO & Architecture by user2525 (1.6k points) | 12 views

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Degree of parallelism
How degree of parallelism is N for horizontal micro program and 1 for vertical micro program, please explain

asked Jul 26 in CO & Architecture by Gateuser99 (102 points) | 2 views

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PIPELINE DOUBT
Is time needed for execution in non-pipeline equal to number of stages ??

asked Jul 26 in CO & Architecture by Ritabrata Dey (242 points) | 11 views

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cs501 Advance Computer Architecture TOPIC NAME: •Hard Disk Transfer Time Calculation

asked Jul 25 in CO & Architecture by Unaiza fatima (102 points) | 2 views

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carl hamachar - problem 8.11
A byte-addressable computer has a small data cache capable of holding eight 32-bit words. Each cache block consists of one 32-bit word. When a given program is executed, the processor reads data sequentially from the following hex addresses: 200, 204, 208, ... the cache at the end of each pass through the loop if a direct-mapped cache is used, and compute the hit rate.

asked Jul 24 in CO & Architecture by amit nagarkoti (102 points) | 4 views

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Operand forwarding Self doubt
In RISC PIPELINING operand forwarding is by default . Is it true?

asked Jul 23 in CO & Architecture by Ram Swaroop (171 points) | 5 views

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GATE 2006-08
A CPU has a 32KB direct-mapped cache with 128 byte-block size. Suppose A is a two-dimensional array of size 512 512 with elements that occupy 8 -bytes each. Consider the following C code segments, P1 and P2: P1: for (i=0; i<512; i++) { for (j=0; j<512; j++) { ... Let the number of cache misses experienced by P1 be M1 and that for P2 be M 2. The value of M 1/ M2 is: 0 1/16 1/8 16

answered Jul 16 in CO & Architecture by user2525 (1.6k points) | 20 views

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ALU DATA PATH and FLOATING NUMBERS
Should I consider to put more efforts on ALU DATA PATH and FLOATING NUMBERS from COA in GATE 2020 as I am not getting those topics and not feeling so confident in these topics?

asked Jul 15 in CO & Architecture by kaival (102 points) | 5 views

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Increment operation is incorporated with which instruction ?

answered Jul 12 in CO & Architecture by Alakhator (355 points) | 5 views

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To transfer control back the RET instruction take
To transfer control back the RET instruction take A=1 argument B=2 argument C=3 arguments D=No arguments

answered Jul 12 in CO & Architecture by Alakhator (355 points) | 5 views

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The source register in OUT is
The source register in OUT is A=AL or AX B=AL or AX C=CL or CX D=DL or DX

answered Jul 11 in CO & Architecture by Alakhator (355 points) | 4 views

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Instruction Microoperation Pseudoinstruction Minioperation

answered Jul 11 in CO & Architecture by Alakhator (355 points) | 4 views

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When the operand of DIV instruction is of 16-bits then implied dividend will be stored in______

answered Jul 11 in CO & Architecture by Alakhator (355 points) | 5 views

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