Recent questions and answers in CO & Architecture - GATE CSE Doubts

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Madeeasy Testseries COA Q1
Anyone please clarify..

answered 14 hours ago in CO & Architecture by Abhisheksmile94 (193 points) | 25 views

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Self doubt in instruction execution cycle /(CO) computer organization

asked 1 day ago in CO & Architecture by Kavya sharma (11 points) | 10 views

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ME test series
Which of the following statements are true? S1: Doubling the line size halves the number of tags in the cache. S2 : Doubling the associativity increases the number of tags in the cache. S3 : Doubling the line size usually reduce compulsory misses. How to approach such kind of question?

asked 4 days ago in CO & Architecture by Abhineet Singh (23 points) | 33 views

+1 vote

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ME test series
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are load and store instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles and cache miss rate is 2%. Which of the following are ... misses is 2.9. D CPI for the handling cache hits is 2.45. How to solve this, unable to get any option...

asked 4 days ago in CO & Architecture by Abhineet Singh (23 points) | 38 views

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ME test series
Which of the following are correct?(MSQ) A Compulsory misses can be reduced by increasing the block size. B The search concept used in associative memory is parallel search. C Conflict misses can be reduced by increasing block size. D Reducing block ... spatial locality. I'm having some trouble in approaching these type of questions. Please tell how to solve these type of questions

asked 4 days ago in CO & Architecture by Abhineet Singh (23 points) | 4 views

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VIT University
A number F is represented in floating point notation as a triplet <s,E,M> where s is the sign bit, E is the exponent and M is the mantissa. Consider the floating point representation similar to IEEE-754 but with the following constraints ... exponent is represent as a true exponent without any biasing. Represent the number 75.75 in floating point using the above consideration.

answered 6 days ago in CO & Architecture by Shaik Masthan (1.5k points) | 8 views

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Applied Test Series
For a computer based on 3-address instruction formats, each address field is used to specify which of the following S1: A memory operand S2: A processor register S3: An immediate constant data Which of the following statements are correct? a) Either S1 or S2 b) Either S2 or S3 c) Only S2 or S3 d) All of S1, S2 and S3

answered Jan 8 in CO & Architecture by Sahil91 (645 points) | 29 views

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Source : Applied GATE test series
In a two-level cache system, the access time of the L1 cache is 20ns and L2 cache is 40ns. If the hit rate of L1 is 80% and L2 is 90% and the miss penalty on a cache miss is 10 ns. The average memory access time is________ (nsec) a. 28.2 b. 23.4 c. 25.6 Please provide the formula and proper explanation of solution.

answered Jan 8 in CO & Architecture by Abhisheksmile94 (193 points) | 28 views

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Applied Gate Grand Test
Consider the following fragment of MIPS code: sw r16,12(r6) lw r16,8(r6) beq r5,r4,Label # Assume r5!=r4 add r5,r1,r4 slt r5,r15,r4 What are the total number of cycles for this instruction sequence in the 5-stage(IF, ID, EX, MEM, WB) pipeline that only has one memory.

asked Jan 7 in CO & Architecture by anurags228 (23 points) | 8 views

+1 vote

1 answer

Gate Academy
Q.Considerhe following program segment hypothetical CPU have three resistors r1 r2 and r3 | Instruction operation Instruction size (in word) Mov r1,5000 r1<- memory [5000] 2 Mov r2(r3) r2<- memory [r1] 1 Add r2 r3 r2<- r2+r3 1 Mov 6000 ... cycle per word Instruction fetch and decode: 2 clock cyxle per word The total number of clock cycle required to execute the program is?

answered Jan 6 in CO & Architecture by zxy123 (2.9k points) | 30 views

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Applied course test series : DRAM chips
Consider a main memory constructed with Synchronous DRAM chips that have the following timing requirements : 1 bus cycle to transfer the address , 10 bus cycles access latency , and 1 bus cycle to transfer a word . Assume that 32 bits of data ... take to access and transfer 32 bytes of data? (in nanosecond) What will be the correct answer for above question?

answered Jan 4 in CO & Architecture by mohan123 (21 points) | 93 views

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Ace Subject Wise Test CO

answered Jan 3 in CO & Architecture by Sahil91 (645 points) | 18 views

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1 answer

Made Easy Test Series
Why 21 is not an answer?

answered Jan 2 in CO & Architecture by zxy123 (2.9k points) | 45 views

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Made Easy Test Seires
Can Anyone Explain why an Extra page fault is there?

asked Jan 2 in CO & Architecture by Parth27 (9 points) | 16 views

+1 vote

1 answer

Applied Gate Topic Wise test

answered Dec 29, 2020 in CO & Architecture by wander (287 points) | 64 views

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Gre cse question
Gre computer architecture question

asked Dec 29, 2020 in CO & Architecture by Amit puri (5 points) | 9 views

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Gre pipelinimg
Plz post thr solution

asked Dec 29, 2020 in CO & Architecture by Amit puri (5 points) | 9 views

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#coa #made-easy #pipelining
Consider the following sequence of instructions: I1: LOAD R4, 0(R8) //Loading the content of M[R8+0] into the register R4. I2: AND R1, R5, R2 I3: OR R1, R1, R3 I4: OR R2, R2, R7 I5: ADD R3, R2, R1 I6: STORE R3, 0(R8) ... more doubt: if in question they mention to not use operand forwarding . then can we consider spilt phase between WB and ID phase in all such questions.

asked Dec 25, 2020 in CO & Architecture by 404 found (31 points) | 10 views

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Made Easy Test Series
Consider a pipeline X consists of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 6ns, 4ns, 3ns, 7ns and 2ns. The alternative pipeline Y contains the same number of stages but EX stage is divided into 3 sub stages (EX1, ... which are memory based instructions then the speed up ratio of X to speed up ratio of Y is ? (Answer upto 2 decimal places)

answered Dec 25, 2020 in CO & Architecture by Sahil91 (645 points) | 21 views

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Instruction pipeline, data hazards
In data hazards in Instruction pipeline, do we have to consider only adjacent data dependency (like I1- I2) or non adjacent as well(like I1-I5) for any of RAW, WAR, WAW

asked Dec 24, 2020 in CO & Architecture by Vishal Saha (5 points) | 2 views

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GeeksforGeeks
Consider a RISC pipeline having 5 stages (instruction fetch, decode, Execute, Memory, Write back), Find how many cycles are required for the instruction given below, assume operand forwarding, branch prediction is used in which the branch is not taken and BEQ is the branch instruction. I1: BEQ R0, R1,X ... I4: X: ADD R5, R1, R2 I5: LOAD R1, 0(R5) I6: SUB R1, R1, R4 I7: ADD R1, R1, R5

asked Dec 22, 2020 in CO & Architecture by AMANGOEL007 (5 points) | 7 views

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Unacademy Free Test COA Q1
There is a system that uses 24 bits of instructions and 10-bits addresses. It supports 2- address and 1-address instructions both. Suppose there are maximum possible 1-address instructions are a, and minimum possible 1-address instructions are b. Then the maximum value of a – b is _________?

answered Dec 21, 2020 in CO & Architecture by wander (287 points) | 21 views

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PYQ Doubt. source: https://gateoverflow.in/863/gate2002-10

answered Dec 17, 2020 in CO & Architecture by gajendercse (41 points) | 23 views

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base conversion question.
$(142)_b + (112)_{b-2}=(75)_8$, find base b How to solve these type of question fast

answered Dec 16, 2020 in CO & Architecture by zxy123 (2.9k points) | 17 views

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Made easy Test Series
Consider a write through cache memory having the hit ratio for read operation 80% and access time of 50 ns. Main Memory access time is 200 ns. CPU generates 70% read requests and remaining are used for write operations. What is the average ... organization and showing answer as 116 ns. I am confused when to use hierarchial organization and when to use simultaneous access)

asked Dec 10, 2020 in CO & Architecture by FreddieMercury (5 points) | 8 views

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Explain Cycle Stealing in DMA?
Can you give me any sources that explain what cycle stealing is? Or explain it?

asked Dec 9, 2020 in CO & Architecture by siddharths067 (10 points) | 11 views

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Ace test Series
Hi, Should not we solve it like..instructions from 1-15 = (k+n-1) = 5 + 14 = 19, assuming branch takes at exe stage so 3 stall cycle then instructions from 75-100 will take 26 clock cycles.. I feel the question is incorrect. Please help me with this doubt..

asked Dec 8, 2020 in CO & Architecture by vipin.gautam1906 (5 points) | 13 views

+1 vote

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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase!

asked Dec 8, 2020 in CO & Architecture by HitechGa (9 points) | 13 views

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Applied Course Test Series Computer Organisation
Consider a processor where each instruction takes, on average, 2 cycles and there are 1.5 references to memory per instruction. A program with 100,000 instructions is executed on this machine using a split cache of 32KB, obtaining a ... processor is adjusted to match the cache hit latency. The Execution time for the smaller cache is________(in µs).

answered Dec 5, 2020 in CO & Architecture by Sahil91 (645 points) | 34 views

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Applied Gate Test Series Computer Organisation
Consider the following CPU base CPI = 1, clock rate = 4GHz Miss rate/instruction = 2% Main memory access time = 100ns then the effective CPI for the given cache is_____________

answered Dec 5, 2020 in CO & Architecture by Sahil91 (645 points) | 28 views

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Made Easy Test
can someone tell weather to take local miss rate or the global miss rate???

asked Dec 5, 2020 in CO & Architecture by Ashutosh777 (-219 points) | 17 views

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Gate Overflow Doubt ques
https://gateoverflow.in/30994/direct-mapping-and-types-of-misses can someone explain how are they calculating the capacity misses and how 4 is not a capacity miss

asked Dec 4, 2020 in CO & Architecture by Ashutosh777 (-219 points) | 20 views

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Made Easy Test Series 2020 - FLT 4 (BASIC)
What is the meaning of the overlapped here? i didnt get this one. Please give solution

answered Dec 2, 2020 in CO & Architecture by _sajalrai_ (563 points) | 48 views

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Applied Subject Wise
https://drive.google.com/file/d/1u7M2dlAzxFIuRKlRadhsSFtf0hAVOKRi/view?usp=sharing : for clear photo here they considerd the memory as word addressable and no of add feild bits =log2(128k) but here https://csedoubts.gateoverflow.in/21470/made-easy-test-series they have calculate the memory size log2(64K*2B) what is right??

answered Dec 1, 2020 in CO & Architecture by _sajalrai_ (563 points) | 28 views

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MadeEasy-TESTseries
I am getting 1.15 as a answer? is the given answer to this correct?

asked Nov 30, 2020 in CO & Architecture by Sinchit (17 points) | 18 views

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Platform Technologies
Pretend you are ready to buy a new computer for personal use. First, take a look at ads form various magazines and newspapers and list items you don't quite understand. Look these terms and give a brief written explanation. Decide what factors are ... them. After you select the system you would like to buy, identify which terms refer to hardware and which refer to software.

asked Nov 29, 2020 in CO & Architecture by ragnarok_29 (5 points) | 11 views

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1 answer

Comparators and Multiplexers in all three Caches
Can anyone give the crisp conclusion on number of comparators and multiplexers required for Direct mapped cache k-way set associative Cache Fully set associative cache Please include diagrams and explanation. Note: you can also refer Hamacher.

answered Nov 26, 2020 in CO & Architecture by zxy123 (2.9k points) | 56 views

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#COA #made-easy
A cache has a hit rate of 95% ,128-byte lines,and a cache hit latency of 5ns .the main memory takes 100ns to return the first word(32 bits) of a line,and 10ns to return each subsequent word .what is the cache miss penality of this system ? (assume that the ... has been fetched and then re-executes the memory operation). a)400ns b)410ns c)415ns d)420ns ans is d but i am getting b.

asked Nov 25, 2020 in CO & Architecture by 404 found (31 points) | 15 views

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1 answer

GATE CS Applied Course
Consider the following fragment of MIPS code: sw r16,12(r6) lw r16,8(r6) beq r5,r4,Label # Assume r5!=r4 add r5,r1,r4 slt r5,r15,r4 What are the total number of cycles for this instruction sequence in the 5-stage(IF, ID, EX, MEM, WB) pipeline that only has one memory. Please explain the approach here

answered Nov 23, 2020 in CO & Architecture by zxy123 (2.9k points) | 48 views

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1 answer

answered Nov 20, 2020 in CO & Architecture by zxy123 (2.9k points) | 21 views

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