Recent questions and answers in CO & Architecture - GATE CSE Doubts

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telegram internet

asked 6 days ago in CO & Architecture by Love Barot (7 points) | 19 views

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Interrupt Service
In which cases does the CPU halts the currenty executing instruction and service the interrupt? and in which case does it first finishes the execution of the current instruction and then service the interrupt.

asked 6 days ago in CO & Architecture by learner 2102 (5 points) | 8 views

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applied gate test series
Two disk drives are available for a particular computer. Disk A has 5400 rpm and drives B has 7200 rpm. Which disk drive provides better performance? a) Drive A b) drive B c) Both have the same performance d) Insufficient information to decide

asked Oct 21 in CO & Architecture by CSHuB (13 points) | 11 views

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NPTEL Self-doubt
A device with transfer rate of 20KBPS is connected to a CPU. Data is transferred byte wise. Let the interrupt overhead be 6microsec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt-driven mode?

answered Oct 19 in CO & Architecture by spike500 (17 points) | 17 views

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DUET MSc Computer Science 2020
An instruction is stored at location 500 with its address field at location 501. The address field has the value 300. The processor register R1, Base Register BR and Index Register XR contain the values 200, 350 and 100 respectively. What is the effective address (EA) if the addressing mode of the instruction is Indexed ?

answered Oct 19 in CO & Architecture by spike500 (17 points) | 8 views

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DUET MSc Computer Science 2020
A 32 bit computer uses a memory unit with 2048 K storage cells. A binary instruction code is stored in one word of memory. The instruction has 4 parts: an indirect bit, an operation code, a register code part to specify one of 63 registers and an address part. How many bits are there in the operation code and the register code part?

answered Oct 19 in CO & Architecture by spike500 (17 points) | 7 views

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Made Easy topicwise coa
please someone explain me option (a) is it correct or not with explanation?

asked Oct 18 in CO & Architecture by Ashutosh777 (67 points) | 9 views

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Made Easy Topic Wise COA
in these kind of ques i always get confused weather to use x/x+y or x/y?? y = time taken by io device to prepare data. and x=time taken by cpu in interrupt processing

asked Oct 18 in CO & Architecture by Ashutosh777 (67 points) | 9 views

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vectored Interrupts
In non vectored interrupts interrupting device send the ISR address but on internet it is as follows: Non-vectored interrupt is an interrupt that has a common ISR, which is common to all non-vectored interrupts in the system. Address of this common ISR is known ... is obtained from a register in the processor D. None of the above Answer is B why? please clear my doubts Thank You

asked Oct 17 in CO & Architecture by ma1999 (5 points) | 7 views

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Made Easy Test Series
What would be the answer? I am getting 100.

answered Oct 17 in CO & Architecture by mayureshpatle (855 points) | 41 views

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Made easy test Series 2020
Consider the following sequence of instructions executed on a 5 Stage pipeline(IF,ID,EX,M,WB). Data Dependency is resolved using the Operand forwarding technique. MOV instruction output is present in the 4th stage and ALU operation output in the 3rd stage I1: ... MUL R2, R3 What is the no. of cycles required to complete the program? (Assume each stage takes 1 cycle time)

asked Oct 16 in CO & Architecture by Gautam9596 (5 points) | 17 views

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Chapter Name: Secondary Memory
I’m not understand the given question. please solve and give me the brief explaination.

asked Oct 15 in CO & Architecture by M Vinod Kumar (5 points) | 11 views

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Made Easy Test Series 2020
The control field of the one-address control word has to support 2 Groups of control signals. It requires to generate either 1 or none of the 70 control signals in the Group1. In Group 2 at most 4 from the remaining. The minimum and maximum no. of bits needed for the control field is ___ and ____ respectively

asked Oct 15 in CO & Architecture by Gautam9596 (5 points) | 12 views

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Made Easy - COA TEST

asked Oct 15 in CO & Architecture by prajjwalsingh_11 (13 points) | 31 views

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When should we take equal clock cycles in pipeline questions and when we shouldn't?

asked Oct 12 in CO & Architecture by VYAN_jy (5 points) | 8 views

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NPTEL ASSIGNMENT QUESTION
A DMA controller transfers 32-bit words from an input device to memory in one clock cycle using cycle stealing. The input device transmits data at a rate of 9600 bytes per second. The CPU is fetching and executing instructions at an average rate of 2,000,000 ... instructions). The CPU will be slowed down because of the DMA transfer by ................. percent.

answered Oct 11 in CO & Architecture by HeartBleed (79 points) | 18 views

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GATEBOOK TEST - TOC Q-7
Suppose there are four languages . Each of the languages may or may not be recursive enumerable. However, we know that the following about them: There is a reduction from to There is a reduction from to There is a reduction from to Below are four statements. Indicate whether each one is (a) CERTAIN to be true, ... C) P-(c), Q-(b), R-(a), S-(a) (D) P-(c), Q-(b), R-(a), S-(b)

asked Oct 7 in CO & Architecture by Gate2022 (7 points) | 12 views

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GATEBOOK Test Series - TOC Q 14
Let h be the homomorphism defined by h(a) = b and h(b) = a. Let Which of the following statements is correct? (A). L is regular. (B). L is non regular DCFL (C). L is non-DCFL But CFL (D). L is Non-CFL

asked Oct 7 in CO & Architecture by Gate2022 (7 points) | 39 views

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GATEBOOK TEST SERIES - TOC - Q17
Consider the following problems. 1. Given a TM M and a string w, does M ever write the symbol ... of the above problems are decidable? (A) Only 4 (B) 2 and 3 Only (C) 2 and 4 Only (D) 2, 3 and 4 Only

asked Oct 7 in CO & Architecture by Gate2022 (7 points) | 11 views

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Gatebook test pipeline
A 7 stage pipeline with following stage delays 100, 150,190,200,400,250,350 is changed to 5 stage pipeline with 100, X, 150, 140, 200 to increase the speed up percentage to 100 percent. The main reason to move to a lesser no of stages is the efficiency of the 7 stage pipeline was only 40 %. What is the maximum value X can take?

asked Oct 6 in CO & Architecture by Raj_81 (5 points) | 18 views

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Applied CO topic wise test
A 5 staged pipelined processor has the stages , Instruction fetch(IF) , Instruction Decode(ID) , Execute(EX) ,Memory(MA) , and Write back(WB) . The number of clock cycles needed to execute the following sequence of instructions is - (Assume that no operand ... R1, R1, R4 In this question, test Series answer is given 14, but I am getting 17 cycles, Can anybody verify it.

answered Oct 6 in CO & Architecture by Shashank Rustagi (513 points) | 33 views

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Self Doubt - percentage of time CPU is busy or idle in different modes

asked Oct 5 in CO & Architecture by smn98 (5 points) | 21 views

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Applied test
Where am I doing wrong? my sol : I1-I2($1) I1-I5($1) I2-I3($2) I3-I5($1)

asked Oct 5 in CO & Architecture by Raj_81 (5 points) | 16 views

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computer Architecture
standard book for the computer architecture? especially clearing the concept for the memory organization ??

answered Oct 4 in CO & Architecture by SarathBaswa (337 points) | 13 views

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self doubt on pipelining
In the questions of pipelining if question doesn’t mention anything about using operator forwarding then in that case what we should do means whether we have to solve the question by considering operator forwarding or without operator forwarding?

asked Oct 4 in CO & Architecture by 404 found (11 points) | 17 views

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DMA burst mode
i have solved so many question related to DMA particulary burst Mode and cycle stealing mode, my doubt is when cpu relinquish the bus control , now in burst mode data is transmitted from Disk Buffer to memory..is it happening on disk transfer rate or is it happening at memory bus transfer rate

asked Oct 3 in CO & Architecture by Sneha negi (5 points) | 7 views

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#madeeasy-test-series #COA
Consider a 5 stage pipeline with IF, ID, EX, MEM and WB latencies 8, 6, 10, 6 and 4 respectively (in ns). If EX stage is made 100% faster, the percentage it will improve the performance CPU is __________%.

asked Sep 27 in CO & Architecture by 404 found (11 points) | 18 views

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Input output interface made easy workbook
Which of the following statements true about firewire 1. The firewire interface is a high speed serial interface that transfer data is packets. 2. The firewire interface can use a daisy chain or free configurations. (a) Only 1 (b) Only 2 (C) Both 1 and 2 (d) Neither 1 nor 2

answered Sep 25 in CO & Architecture by Nitinkumar.097 (11 points) | 19 views

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GO-gate-pyq-ques
https://gateoverflow.in/8215/gate2015-2-42 in this ques total 4bytes means 32 bits has to be added into the 016E but we are adding just 4 bits and ans is 0172. 0000 0001 0110 1110 0000 0000 0010 0000 0000 0001 1000 1110 it should be 018E i know i am going wrong somewhere but please someone clear this

asked Sep 23 in CO & Architecture by Ashutosh777 (67 points) | 21 views

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GATE2005-IT-49 Video Solution
An instruction set of a processor has $125$ signals which can be divided into $5$ groups of mutually exclusive signals as follows: Group $1$ $:$ $20$ signals, Group $2$ $:$ $70$ signals, Group $3$ $:$ $2$ signals, Group $4$ ... . How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming? $0$ $103$ $22$ $55$

answered Sep 22 in CO & Architecture by Deepak2323 (5 points) | 18 views

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Self doubt on number of data dependencies
What is the answer for this question - https://gateoverflow.in/29896/number-of-war-dependencies 9 or 11?

asked Sep 20 in CO & Architecture by nvs16 (9 points) | 12 views

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Self Doubt on pipelining and flow dependency
Does true/flow dependency always produce one or more stalls in the pipeline?

asked Sep 20 in CO & Architecture by nvs16 (9 points) | 10 views

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Self doubt in instructionpipeline.
In a 5 stages pipeline named as IF,ID,OF,MR,WB.in order to execute I1:load r0,3(r1) I2:add r3,r2;r0. l3:sub r4,r3,r5; I4:mul r6,r4,r7; can we execute OF and MR or OF and EX stage in the same clock cycle given that the operand forwarding is used.if every stage takes 1 clk cycle then how long will take it to complete the above instruction in the pipeline

asked Sep 18 in CO & Architecture by Kavya sharma (11 points) | 11 views

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# Made Easy Test
[closed]

asked Sep 15 in CO & Architecture by raviranjan21 (5 points) | 21 views

+1 vote

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Self Doubt on Addressing Mode in COA
I read in some gateoverflow answer that register address mode is used for local variables and direct address mode is used for global variables. Why are local variables stored in registers? Arent they part of the activation record which gets ... C programming language there is a special keyword register to store the variable in register. Am I missing something?

answered Sep 15 in CO & Architecture by gatecse (173 points) | 65 views

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Made easy coa workbook
Suppose DMA is employed in cycle stealing mode and transfer of bus control from CPU to 1/O or 1/O to CPU takes 300 ns. Assume the system in which bus cycle takes 700 ns, and one of the I/O device has a data transfer rate of 50 KB/sec and employs DMA. Data are transferred ... the 1/O device to transfer a block of 100 bytes? (Approx.) (a) 100 us (B) 120 us (C) 110 us (d) 130 us

answered Sep 12 in CO & Architecture by gajendercse (11 points) | 22 views

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#selfdoubt #CO
What is the difference between Micro Program Counter and Control Address Register?

asked Sep 10 in CO & Architecture by Dheeraj Varma (13 points) | 9 views

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Made Easy, COA Subject wise test 2 | Cache Memory
A cache has a hit time of 10ns and hit rate of 60%. An optimization was made to increase the hit rate to 70%, but the hit time also got increased to 15ns. The optimization resulted in 10% reduction in average memory access time. Assume that the miss penalty is unaffected by the optimization. The miss penalty of the cache (in ns) is___?

answered Sep 9 in CO & Architecture by KUSHAGRA गुप्ता (1.4k points) | 26 views

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Made Easy COA Subject Wise
Consider a two level cache memory organization. L1 has an accessing time 30 ns and main memory access time 200 ns. Assume the hit ratio for read operation is 0.65 and 45% reference are for the write operation. The average access time for system(in ns) if it uses write through technique __________.

answered Sep 8 in CO & Architecture by akashmittal1208 (71 points) | 74 views

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Made Easy Subject Wise COA
Consider 2 MBPS I/O device interfaced to 64 bit CPU in a programmed I/O mode. Data transmission between the CPU and I/O in word wise. interrupt overhead is 3 μ sec. What is the performance gain when the device is operating under interrupt I/O over programmed I/O mode? (Please suggest some resource also to study for this topic)

answered Sep 8 in CO & Architecture by KUSHAGRA गुप्ता (1.4k points) | 45 views

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