Recent questions and answers in CO & Architecture
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Recent questions and answers in CO & Architecture

Recent questions and answers in CO & Architecture
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0 answers 37 views
#COA #TEST-SERIES
A particular parallel program computation require 200 seconds when it is executed on a single processor. If 40% of this computation is “inherently sequential” then what are the theoretically best elapsed time for this program running with 2 and 4 processors respectively? A.80 and 120 seconds B.90 and 60 seconds C.140 and 110 seconds D.100 and 80 seconds
Abhishek tarpara asked in CO & Architecture Sep 4, 2021
by Abhishek tarpara
13 points
37 views
0 votes
0 answers 46 views
#Madeeasy #COA #page-replacement #cache-memory
Consider a direct mapped cache with 16 blocks with block size of 16 bytes. Initially the cache is empty. The following sequence of access of memory blocks: Ox80000, Ox80008, Ox80010, Ox80018, Ox30010 is repeated 10 times. Which of the following represents ... = 3 and conflict = 18 C.Compulsory = 4 and conflict = 16 D.Compulsory = 2 and conflict = 20
Abhishek tarpara asked in CO & Architecture Sep 4, 2021
by Abhishek tarpara
13 points
46 views
0 votes
0 answers 52 views
pipeline-Hazard
Our system has single memory port, but a separate port is available dedicated to the stack.Note that out instruction uses an I/O port isolated from the memory. We need to find the type of hazards possible in the following . SOLUTION: Instruction 2, 3 has data ... dependency hazard because of bx I came up with this answer, please can you guide me if i am wrong or missed something.
Autumn asked in CO & Architecture Sep 1, 2021
by Autumn
71 points
52 views
0 votes
0 answers 45 views
Pipeline-hazard
Question: Consider the code sequence shown below running on the basic 5-stage instruction pipeline. Each stage takes 1 cycle without hazards. The pipeline stalls on data dependencies that cannot be fully resolved by forwarding. Load instructions do not have delay slots ... of cycle it take to complete ANSWER: Can you please guide me with the below solution, where it goes wrong.
Autumn asked in CO & Architecture Sep 1, 2021
by Autumn
71 points
45 views
0 votes
0 answers 63 views
COA gate 2022
Do we need to learn both x86 and ARM architecture for gate 2022? Or only x86?
Shivam_j asked in CO & Architecture Aug 26, 2021
by Shivam_j
5 points
63 views
0 votes
0 answers 19 views
Self doubt
Can memory read and memory write operations be performed at the same time ?
Krishnendu_01 asked in CO & Architecture Aug 19, 2021
by Krishnendu_01
5 points
19 views
0 votes
0 answers 40 views
gatebook test series
Which of the following statements about caches is (are) true? I. A direct-mapped cache can have a lower miss rate than an associative cache of the same size (number of blocks). II. Programs with high spatial locality have a low cache miss rate primarily because the exact same ... addresses are re-referenced. A) III only B) I and III only C) II and III only D) I , II, III ALL
farmanahmed888 asked in CO & Architecture Aug 17, 2021
by farmanahmed888
5 points
40 views
0 votes
0 answers 90 views
Self Doubt
What is Size of Multiplexer in direct mapping. Tag bit is 10 bits .And word offset is 1 bits.
DKY123 asked in CO & Architecture Aug 9, 2021
by DKY123
15 points
90 views
0 votes
0 answers 51 views
geeks for geeks quiz
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown : What is the number of cycles needed to execute the following loop? for (i = 1; i < = 1000; i++) {I1, I2, I3, I4}
swami_9 asked in CO & Architecture Jul 22, 2021
by swami_9
5 points
51 views
0 votes
0 answers 57 views
COA Test Series
A byte addressable computer has a small data cache capable of holding sixteen 32 bit words. Each cache block consist of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4 way set associative LRU cache is used is ________. (Upto 1 decimal places) 100, 104, 108, 104, 107, 108, 105, 102, 108, 103
Abhishek tarpara asked in CO & Architecture Jul 18, 2021
by Abhishek tarpara
13 points
57 views
0 votes
0 answers 22 views
grade up quiz
A computer system with a word length of 32 bits has a 16 MB word- addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation. A1 = 0x42C8A4, A2 = ... same cache set. C A3 and A4 are mapped to the same cache set. D A1 and A3 are mapped to the same cache set.
swami_9 asked in CO & Architecture Jul 14, 2021
by swami_9
5 points
22 views
0 votes
0 answers 24 views
Self doubt from coa
“Stack pointer is decremented locally” What does this mean? This was present in one of the previous year gate question on topic control unit design
Harshad_Shinde asked in CO & Architecture Jul 13, 2021
by Harshad_Shinde
5 points
24 views
0 votes
0 answers 35 views
MadeEasy Postal Package Question Bank
Determine the width of Micro-instruction having following Control signal field, in a Vertical Microprogrammed Control Unit 1. Next Address field of 7 Bits 2. ALU Function field selecting 1 out of 13 ALU Function. 3. Register-in field selecting 1 out of 13 ALU Function. ... shift or left shift. 6. Auxiliary control field of 4 bits. (a) 22 (b) 23 (c)24 (d) 25
Ranjul Bandyopadhyay asked in CO & Architecture Jul 8, 2021
by Ranjul Bandyopadhyay
7 points
35 views
0 votes
0 answers 31 views
computer architecture
Discuss the effect of changing the order of the second loop (for i := 0 to 9 do) of the program discussed in class to elaborate various cache mapping schemes. Re-write the tables how cache is filled for all mapping schemes and comment on performance. If performance deteriorates how can it be improved.
harram asked in CO & Architecture Jul 6, 2021
by harram
5 points
31 views
0 votes
0 answers 33 views
Lecturer In Information Technology KPSC-2015
Which is true for typical RISC architecture? A.Micro Programmed Control Unit B.Instruction takes multiple clock cycles. C.Have few register in CPU D.Emphasis on optimising instruction pipelines
Midhun K R asked in CO & Architecture Jun 18, 2021
by Midhun K R
5 points
33 views
0 votes
0 answers 54 views
GATE previous year question
consider a direct mapped cache of 8 blocks used to implement the following program segment float a[10][10]; int i; for(i=0;i<10;i++) for(j=0;j<10;j++) a[i][j]=8.0; float element occupies 4 bytes, the block size is 12 bytes and ... in row-major form. Find the number of hits. also, if the array was stored in coloumn-major, What the number of hits would've been?
donniedarko asked in CO & Architecture Jun 12, 2021
by donniedarko
39 points
54 views
0 votes
0 answers 26 views
My final exam
Suppose our computer requires 2048x16 bytes of RAM and 512x16 bytes of ROM. Design the necessary hardware using 512x16 byte RAM and 256x16 byte ROM chips
AliOzmaral asked in CO & Architecture Jun 7, 2021
by AliOzmaral
5 points
26 views
0 votes
0 answers 42 views
Made Easy Workbook
Consider a machine with a byte addressable main memory of 2^16 bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. A 50 x 50 twodimensional array of bytes is stored in the main memory starting from memory location 1100 H. Assume that ... (a) line 4 to line 11 (b) line 4 to line 12 (c) line 0 to line 7 (d) line 0 to line 8
grv_d asked in CO & Architecture May 6, 2021
by grv_d
9 points
42 views
0 votes
0 answers 64 views
Made easy workbook
A three level memory system having cache access time 15ns and disk access time 80ns cache hit ratio is 0.96 and main memory hit ratio is 0.9 What should be v main memory access time to achieve effective access time of 25ns
Young Stunner asked in CO & Architecture Apr 14, 2021
by Young Stunner
5 points
64 views
0 votes
0 answers 60 views
In a computer system, the cache memory uses two-way set associative mapping technique to do the address translation.
Aman Patel asked in CO & Architecture Apr 2, 2021
by Aman Patel
5 points
60 views
0 votes
0 answers 38 views
Nptel noc19_cs03 Assignments
The clock rate of a machine depends on: a. Cpu Organisation b. Instruction set Architecture. c. Implementation Technology. d. Assembler
Yashvir asked in CO & Architecture Mar 18, 2021
by Yashvir
5 points
38 views
0 votes
0 answers 137 views
CO & Architecture Work book chapter Machine instruction and addressing modes
Nitinkumar.097 asked in CO & Architecture Mar 3, 2021
by Nitinkumar.097
13 points
137 views
1 vote
0 answers 720 views
GATE CSE 2021 Set 2 | Question: 27 | Video Solution
Arjun asked in CO & Architecture Feb 18, 2021
by Arjun
1.4k points
720 views
0 votes
0 answers 31 views
Where to read Cache Memory concept ?
Hi, my concepts regarding cache memory is weak. Please let me know that where (book or online source) to read Cache memory concepts ? If you have any knowledge about it please share ? Please try to share only standard sources.
beta asked in CO & Architecture Feb 17, 2021
by beta
5 points
31 views
0 votes
0 answers 37 views
Self doubt COA
How to know when to use simultaneous average time formula and when to use hierarchical average time formula for the calculation of tavg questions?
Abhipsa asked in CO & Architecture Feb 10, 2021
by Abhipsa
17 points
37 views
1 vote
0 answers 27 views
MADEEASY TEST SERIES
https://gateoverflow.in/3622/gate2006-it-78 with reference to the concept used in previous year question the answer for the true data dependencies in the following question should be 5 ?? but solution is given as 3... M[100<-r1 r2<-M[700] r1<-r2 / r1 r2<-r1+r2 M[500]<-r2 M[200]<-r1
eyeamgj asked in CO & Architecture Feb 9, 2021
by eyeamgj
29 points
27 views
0 votes
0 answers 42 views
Ace Pre GATE 2021
Could someone tell why option C and D are wrong A) B ) C ) D ) Correct Answer: A,B Your Answer: A,B,C,D
RohitRo45 asked in CO & Architecture Feb 6, 2021
by RohitRo45
5 points
42 views
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