# Recent questions and answers in CO & Architecture

Which is true for typical RISC architecture? A.Micro Programmed Control Unit B.Instruction takes multiple clock cycles. C.Have few register in CPU D.Emphasis on optimising instruction pipelines
consider a direct mapped cache of 8 blocks used to implement the following program segment float a[10][10]; int i; for(i=0;i<10;i++) for(j=0;j<10;j++) a[i][j]=8.0; float element occupies 4 bytes, the block size is 12 bytes and array is stored in row-major form. Find the number of hits. also, if the array was stored in coloumn-major, What the number of hits would’ve been?
Suppose our computer requires 2048x16 bytes of RAM and 512x16 bytes of ROM. Design the necessary hardware using 512x16 byte RAM and 256x16 byte ROM chips
The value represented by the following 32-bits in IEEE-754 standard is? 0100000111100000……00
Suppose we are using the paging concept. The CPU generates an logical address Now suppose in the memory page table for the page required by the CPU the presence bit is 0 then how does the CPU get the required page from the secondary memory?
Consider a machine with a byte addressable main memory of 2^16 bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. A 50 x 50 twodimensional array of bytes is stored in the main memory starting from memory location 1100 H. Assume that the data ... array (a) line 4 to line 11 (b) line 4 to line 12 (c) line 0 to line 7 (d) line 0 to line 8
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i need to study COA . can somebody tell me good resources and how to progress with subject
A three level memory system having cache access time 15ns and disk access time 80ns cache hit ratio is 0.96 and main memory hit ratio is 0.9 What should be v main memory access time to achieve effective access time of 25ns
The clock rate of a machine depends on: a. Cpu Organisation b. Instruction set Architecture. c. Implementation Technology. d. Assembler
A PC-relative mode branch instruction is 3 bytes long. The address of the instruction in decimal is 342038. What is the branch address, if the base and index register contains the value 480220 and 9 respectively (Assume base with index addressing mode is used) Answer key says 480198, why?
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ processor. If $0.5 \%$ processor cycles are used for $\text{DMA}$, the data transfer rate of the device is __________ bits per second.
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Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write allocate policy must be ... $S_2$ is false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup}$ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.
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A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.
Consider the following instruction sequence where registers $R1, R2$ and $R3$ are general purpose and $\text{MEMORY}[X]$ denotes the content at the memory location $X$ ... format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________
Hi, my concepts regarding cache memory is weak. Please let me know that where (book or online source) to read Cache memory concepts ? If you have any knowledge about it please share ? Please try to share only standard sources.
How to know when to use simultaneous average time formula and when to use hierarchical average time formula for the calculation of tavg questions?
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https://gateoverflow.in/3622/gate2006-it-78 with reference to the concept used in previous year question the answer for the true data dependencies in the following question should be 5 ?? but solution is given as 3... M[100<-r1 r2<-M[700] r1<-r2 / r1 r2<-r1+r2 M[500]<-r2 M[200]<-r1
Could someone tell why option C and D are wrong A) B ) C ) D ) Correct Answer: A,B Your Answer: A,B,C,D
In RAW dependency , does we consider only adjacent instructions for RAW or we check every instruction present to check for RAW dependency just like WAW and war
Basic pipelining. Use the following code fragment: Loop: LD R2,4(R1) ; load R2 from address 4+R1 LD R3,0(R2) ; load R3 from address 0+R2 DADD R3,R1,R2 ; R3=R1+R2 BNEZ R3,Loop ; branch to loop if R3 != 0 Use the classic MIPS five- ... complete the given sequence of instructions are___ i am getting 9 as answer bit in answer 10 is given can someone explain execution of instruction 4? solution given
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Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions S1 S2 S3 S4 I1 2 1 3 1 I2 1 1 1 3 I3 1 3 2 1 I4 3 1 1 2 What is the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} I am getting answer (20 cycles ) but they gave the answer (23 cycles)
What is the Half Carry in the addition of the two n-bit binary numbers? Suppose two numbers are 00000010 and 00000011 . What is the value of the Half Carry?
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Consider a hypothetical system that uses Direct Memory mode access(DMA) mode to transfer the data from the hard disk to the main memory. If the size of the DMA controller's data count register is 32 bits. A file of 1024 GB needs to transfer from disk to memory. ... the DMA controller needs to get the control of the system bus if the system is byte-addressable? Please explain, the answer was 256.
Consider a cache of 2y blocks, and the main memory of 2y blocks. At what set location (y+4)th block will be mapped in 2-way set associative? In this question, it is asking about (y+4)th block of main memory, then it would be numbered (y+3) in the main memory, so it should get mapped at set location 3. But answer in made easy test is given 4. Is it correct??
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A pipeline with 4 stages :- IF, ID, EX, WB. IF, ID, WB all take 1 cycle each. EX takes 1 cycle for ADD, 1 for SUB, 3 for MUL. Pipeline cycle time is 3 ns. Out of 1000 instructions, 300 are for ADD, 500 are for SUB and 200 are for MUL. Calculate pipeline efficiency Can someone please explain me its solution?
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Consider a write through cache memory having the hit ratio for read operation 80% and access time of 50 ns. Main Memory access time is 200 ns. CPU generates 70% read requests and remaining are used for write operations. What is the average memory ... simultaneous organization and showing answer as 116 ns. I am confused when to use hierarchial organization and when to use simultaneous access)
A 5 stage pipelined processor has the following stages: IF : Instruction fetch, ID : Instruction decode, EX : Execute, MA : Memory access, WB : Write back Number of cycles, using operand forwarding ?
How to calculate memory reference taken by any instruction in the "instruction decode(ID) phase??
Which of the following statements are true? S1: Doubling the line size halves the number of tags in the cache. S2 : Doubling the associativity increases the number of tags in the cache. S3 : Doubling the line size usually reduce compulsory misses. How to approach such kind of question?
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Consider a RISC processor with an ideal CPI, where 25% of the total instructions are load and store instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles and cache miss rate is 2%. Which of the following are correct? ( ... cache misses is 2.9. D CPI for the handling cache hits is 2.45. How to solve this, unable to get any option...