Recent questions and answers in CO & Architecture - GATE CSE Doubts

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Are control word and control data register same thing?

asked 2 days ago in CO & Architecture by namekrakhnu (15 points) | 2 views

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GOF, Made Easy
In this question Arjun sir has used operand forwarding from EX in I3 to EX in I4. Instead, can we think of it like split phase between EX in I3 to ID in I4? https://gateoverflow.in/34735/madeeasy-test-series-co-%26-architecture-pipelining

asked 5 days ago in CO & Architecture by pranavsettaluri9 (6 points) | 5 views

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Where is the cache tag directory data structure stored ?

asked Jul 2 in CO & Architecture by krish71 (6 points) | 8 views

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1 answer

asked in made easy test series
Kindly explained this in detailed way, like why particular steps will come and reason behind it.

answered Jul 2 in CO & Architecture by srestha (755 points) | 30 views

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Made Easy Test Series
Consider 2 MBPS I/O device interfaced to 64 bit CPU in a programmed-I/O mode. Data transmission between the CPU and I/O in word-wise. Interrupt overhead is 3 μ/sec. What is the performance gain when the device is operating under interrup-I/O over programmed-I/O mode? A)2 B)2.5 C)1.33 D)2.66

asked Jul 1 in CO & Architecture by arpit_18 (7 points) | 9 views

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Self doubt : Pipelining hazards
We are having a five-stage RISC architecture pipeline where the stages are instruction fetch ->decode->execute->memory access->write back, in which we are executing a single instruction ADD R1,R2,R3. As we can see that this ... a memory access stage then the total number of cycles required to execute this single instruction is 4 cycles or 5 cycles?

asked Jul 1 in CO & Architecture by bittujash (6 points) | 8 views

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Made easy study material
A three level memory system having cache access time of 15 ns and disk access time of 80 ns has a cache hit ratio of 0.96 and main memory hit ratio of 0.9. What should be the main memory access time to achieve effective access time of 25 ns?

asked Jun 26 in CO & Architecture by premu (73 points) | 17 views

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1 answer

Made easy test series
Consider the type addressable memory unit of a computer has 64 K words of 16 bit each. The computer has an instruction format with 4 fields namely opcode, mode field specify 9-addressing modes, register address field with 50 registers and a memory address field. If an instruction is 32 bits long then the number of different instructions are _____. [closed]

answered Jun 26 in CO & Architecture by Anirban Chand (41 points) | 33 views

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http://www2.cs.siu.edu/~cs401/Textbook/ch3.pdf
in the link http://www2.cs.siu.edu/~cs401/Textbook/ch3.pdf page number 25 has AB = (2,1,0), BA = (4,2,1,0) , so my question is how AB = (2,1,0), BA = (4,2,1,0) ? arjun sir please help .

asked Jun 20 in CO & Architecture by kaushiknits0307 (6 points) | 12 views

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Hit ratio gate question
An access sequence of cache block addresses is of length N and contains n unique block addresses. The number of unique block addresses between 2 consecutive accesses to the same block address is bounded above by k. What is the miss ratio if the access ... associativity A>=k excercising least-recently-used replacement policy? n/N 1/N 1/n k/n Please explain the logic too.

asked Jun 15 in CO & Architecture by Swati Dubey (10 points) | 4 views

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isi 2004 pcb c11

asked Jun 15 in CO & Architecture by tanmoy (14 points) | 3 views

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asked Jun 14 in CO & Architecture by tanmoy (14 points) | 6 views

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computer organization(architecture) question
A computer system has 64KB main memory and 1KB data cache memory. Data transfer between cache and main memory is done using 16 * 8 blocks. The set associative method, which includes 2 blocks in each set (set), is used. LRU (Least ... in the first accesses. During the running of the program, you can show and transfer data between main memory and cache.

asked Jun 12 in CO & Architecture by helixum (6 points) | 17 views

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made easy wb
how to solve questions like this, I got this TAG SETS WORDS 18 7 7

asked Jun 5 in CO & Architecture by ummokkate (64 points) | 14 views

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Made Easy WB
How to use the hit ratio of write access?

asked Jun 5 in CO & Architecture by ummokkate (64 points) | 7 views

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made easy wb
How to solve this question?

asked Jun 5 in CO & Architecture by ummokkate (64 points) | 7 views

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Made Easy WB
How to solve this question?

asked Jun 5 in CO & Architecture by ummokkate (64 points) | 7 views

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MADE EASY WB
I have a doubt in c) part. the bits required for tag are 48bits, the bits required for set are 11bits and bit required for block offset are 5bits

asked Jun 5 in CO & Architecture by ummokkate (64 points) | 6 views

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SELF DOUBT->MISSES IN CACHE
Associative cache: Only compulsory and capacity misses can occur. Direct mapped cache: Only compulasory and conflict misses can occur. Set Associative cache: Compulsory misses occurs. Capacity misses occurs if all the blocks in all the sets are filled. Capacity misses occurs if all the blocks in all the sets are not filled. Please state wheather these are correct or not?

asked Jun 3 in CO & Architecture by Doraemon (115 points) | 7 views

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THE GATEBOOK TEST SERIES
Find the number of data dependencies in the following My doubt here is that while considering the data dependencies do we consider dependencies only in the consecutive instructions or all the instruction. I solved a question from Madeeasy workbook. where they had mentioned we only consider the dependencies from the consecutive instructions only. So I’m a confused...

asked Jun 1 in CO & Architecture by ummokkate (64 points) | 30 views

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Decoder 2-4 connected in parallel in a counter 0-15 (module 16)

asked May 28 in CO & Architecture by ilsiciliano93 (6 points) | 8 views

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Gate cse 2015
Consider a 2 way set associative cache with cache block size 4 bytes total no of data block in cache is 2k(each block is 4 bytes) Cache policy write back, valid =1 per block dirty bit=1 per byte memory address 16 bits. The total size of cache including data and all meta data bits is

asked May 28 in CO & Architecture by Syywyeye (9 points) | 23 views

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Gate cse 2015
If size of cache is 32 bytes and block size is 4 bytes then for the following memory reference :0x00,0x20,0x40,0x80,0x01,0x21,0x41, 0x81 What should be minimum value of k for k way associative cache such that miss rate of cache is 50% and LRU policy is used?

asked May 28 in CO & Architecture by Syywyeye (9 points) | 10 views

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computer system architecture by morris mano third edition chapter 10 question no 7

asked May 23 in CO & Architecture by Bhavya1902 (7 points) | 8 views

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Computer Organization And Embedded Systems Sixth Edition by Carl Hamacher Chapter 1, Problem no. 1.5, Page no. 25.

asked May 16 in CO & Architecture by Gaurav Padole (6 points) | 9 views

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Made easy workbook

asked May 13 in CO & Architecture by ayushayush591 (6 points) | 6 views

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Self Doubt from COA
What would happen if we keep increasing the levels of cache, like 2 level cache is more efficient than 1 level cache so why can’t we have 20 level cache? How will it impact performance . Kindly cite the source for your answer

asked May 12 in CO & Architecture by anurag sharma (13 points) | 9 views

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Computer Architecture doubt
What is the sum of address lines and data lines for the memory $64M \times 32?$ I want to know , why do we need to do bit-Byte conversion here??

asked Apr 27 in CO & Architecture by srestha (755 points) | 12 views

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GATE2020-CS-30 Video Solution
A computer system with a word length of $32$ bits has a $16$ MB byte- addressable main memory and a $64$ KB, $4$-way set associative cache memory with a block size of $256$ ... set. $A3$ and $A4$ are mapped to the same cache set. $A1$ and $A3$ are mapped to the same cache set.

answered Apr 27 in CO & Architecture by amitkhurana512 (189 points) | 14 views

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Gate Questio Cache
Find out the number of page fault in the following strings of pages used by CPU using the page replacement algorithm LRU and LIFO [taking 3 page frames] 1,1,3,5,3,4,2,2,2,1,8

asked Apr 24 in CO & Architecture by Beastm0del (7 points) | 8 views

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Cache Question Gate
A cache consists of a total of 128 blocks. The main memory contains 2K blocks, each consisting of 32 words. ( I )How many bits are there in each of the TAG, BLOCK and WORD field in case of direct mapping? ( ii )How many bits are there in each of the TAG, SET, and WORD field in case of 4-way set-associative mapping?

asked Apr 24 in CO & Architecture by Beastm0del (7 points) | 6 views

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GATE2020-CS-29 Video Solution
Consider three registers $R1$, $R2$, and $R3$ that store numbers in $IEEE-754$ single precision floating point format. Assume that $R1$ and $R2$ contain the values (in hexadecimal notation) $0x42200000$ and $0xC1200000$, respectively. If $R3=\frac{R1}{R2}$, what is the value stored in $R3$? $0x40800000$ $0xC0800000$ $0x83400000$ $0xC8500000$

answered Apr 23 in CO & Architecture by amitkhurana512 (189 points) | 14 views

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GATE2020-CS-44 Video Solution
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction ... two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.

answered Apr 23 in CO & Architecture by amitkhurana512 (189 points) | 14 views

+1 vote

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GATE2020-CS-43 Video Solution
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to ... , the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.

answered Apr 23 in CO & Architecture by amitkhurana512 (189 points) | 12 views

+1 vote

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GATE2020-CS-21 Video Solution
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2$0 ns to bring the first word of a block from the main memory, while ... word takes $5$ ns. The word size is $64$ bits. The average memory access time in ns (round off to $1$ decimal place) is______.

answered Apr 22 in CO & Architecture by amitkhurana512 (189 points) | 49 views

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GATE2004-47 Video Solution
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. ... execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 12 views

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GATE2005-68 Video Solution
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 7 views

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GATE2013-45 Video Solution
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 18 views

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GATE2005-70 Video Solution
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent ... $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2015-3-51 Video Solution
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$. $\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline & \text{1}& \text{2} & \text{$3$} & \text{$4$} & \text{$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______

asked Apr 19 in CO & Architecture by admin (3.6k points) | 4 views

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