Recent questions and answers in CO & Architecture - GATE CSE Doubts

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#microprogrammed control unit
In case of micro programmed control unit, why we have field reserved for control memory address as the micro program counter will automatically be incremented by clock and will point to the next micro instruction in sequence?

asked Mar 30 in CO & Architecture by Lovejeet Singh (7 points) | 4 views

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Self Doubt: Cost Criteria
I understand that gate input cost (G) is the number of inputs to the gates in the implementation corresponding exactly to the given equation or equations and it can be found by finding the sum of all literal appearances and the number of terms excluding single literal ... the gates in the implementation is 0. Which one is the correct gate input cost of F = x'? 1 or 0?

asked Mar 28 in CO & Architecture by Will12 (6 points) | 2 views

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NIELIT-2017-113
The addressing mode used in an instruction of the form $ADD\ X\ Y,$ is ___________ (A) Direct (B) Absolute (C) Indirect (D) Indexed

asked Mar 26 in CO & Architecture by habedo007 (6 points) | 22 views

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Computer Architecture
Suppose that a machine A executes a program with an average CPI of 3. Consider another machine B (with the same instruction set and a better compiler) that executes the same program with 10% less instructions and with a CPI of 1.5 at 1.5 GHz. The clock rate of A so that the two machines have the same performance is _______ GHz.

answered Mar 25 in CO & Architecture by toxicdesire (293 points) | 17 views

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MORRIS MANO(self doubt)
if we have 2 opeartions DR<-AC AND AC<-DR In Morris Mano it has been told that both the operations can be done simultaneously. The contents of AC will be passed to DR through the BUS and the content of DR will be passed to AC using the ALU. ... is there any chance by which the value of AC first gets modified and then the modified value of AC is passed on to DR?

asked Mar 23 in CO & Architecture by Doraemon (101 points) | 5 views

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Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

answered Mar 23 in CO & Architecture by !KARAN (351 points) | 15 views

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Gradeup gate mock
A pipelined processor uses 5 stages with execution time of 3,4,3,2,4 cycles respectively .the corresponding non-pipelined processor uses 8 clock cycles to complete an instruction (ignore buffer delay).Calculate speedup assuming that a very large no. Of instructions are executed . A) 2 B) 3 C) 5 D) 4

answered Mar 18 in CO & Architecture by smsubham (64 points) | 7 views

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APPSC Polytechnic Lecturer
You are designing a microprocessor and restricted to have only four bits in the flag register. What are the flags that you should provide in this case considering the most frequently used flags that are needed in a general computing applications? 1) sign, ... , parity , overflow 2)parity ,zero,sign,overflow 3) sign,zero,overflow,carry 4) carry, auxilary carry, parity,sign

asked Mar 16 in CO & Architecture by Manohar Reddy! (6 points) | 2 views

+1 vote

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Made easy Postal package
A Cache has 64 kB capacity 128 byte line and is 4 way set associative The system containg cache uses 32 bit address If cache is write through _ bits are req for tag entry and total storage req is __ if LRU policy js used a 20,974 21,456 b 10,572 11,264 c 10,572 21,456 d 20,974 11,264

asked Mar 8 in CO & Architecture by simar11498 (7 points) | 11 views

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fully associative mapping?
why do we need to compare the block number from main memory with tag number from cache memory in fully associative mapping? what i have understood? ans-: whenever there is a cache miss i.e data required for the processor is not available in ... block from main memory was not available in cache memory..so what is the point with comparing tag number with block number?

asked Feb 16 in CO & Architecture by namekrakhnu (14 points) | 4 views

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ME test series FLT
In Made Easy solution they have taken Fetch-Decode and Execute stage separately. But why they should consider that? I think their solution not correct. right??

asked Feb 6 in CO & Architecture by srestha (683 points) | 48 views

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ACE TEST SERIES 2017 DEPENDENCY PROBLEM
WHICH OF THE FOLLOWING DEPENDENCY PROBLEM CAN BE ELIMINATED BY USING REGISTER RENAMING? A)DATA DEPENDENCY B)RESOURCE CONFLICT C)STRUCTURAL DEPENDENCY D)ANTI DATA DEPENDENCY .we can remove structural dependency by renaming ...and war (anti ) waw(output) ... alone or BOTH C AND D AND ONE DOUBT STRUCTURAL DEPENDENCY IS DUE TO RESOURCE CONFLICT SO B CAN BE ALSO?

asked Feb 6 in CO & Architecture by eyeamgj (41 points) | 24 views

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Applied course test series : DMA tranfer
A computer uses DMA to read from its disk.Suppose that disk has 32 500-byte sectors per track.The disk rotation time is 32 ms.The bus is 32 bits wide, and bus transfer takes 500ns each.The average CPU instruction requires two bus cycles. How much is the CPU slowed down by DMA? Can some one give answer and solution?

asked Feb 5 in CO & Architecture by vishal burnwal (135 points) | 96 views

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MADE EASY : DMA CYCLE STEALING
An $8-Bit$ DMA Device is operating is Cycle Stealing Mode (Single Transfer Mode). Each DMA cycle is of $6$ clock states and DMA clock is $2$ $MHZ$. Intermediate CPU machine cycle takes $2 μs$, the DMA Data Transfer Rate is ?

asked Feb 2 in CO & Architecture by Debapaul (699 points) | 39 views

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Pumping Lemma (self doubt)
I am not able to understand how $r=0^*1 + 0 + 1^* + 10^*1$ has minimum pumping length of 2 as given in https://gateoverflow.in/303738/michael-sipser-exercise . Can someone please explain? Thank you

answered Feb 2 in CO & Architecture by shashin (1.9k points) | 32 views

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pipelining DEPENDENCIES DOUBT
https://gateoverflow.in/192093/computer-organization-pipelining TRUE TRUE TRUE TRUE FALSE ARE THEY CORRECT? PLEASE VERIFY

asked Feb 2 in CO & Architecture by eyeamgj (41 points) | 25 views

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doubt in RAW hazard
does RAW hazard only occurs only for subsequent statements? I1 : R1+R2 – > R3 I2 : R3+ R1 –> R4 I3 : R3 + R4 → R4 isn’t I1 and I3 has RAW dependency.

asked Feb 2 in CO & Architecture by mehul vaidya (22 points) | 43 views

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doubt in RAW hazard
does RAW hazard only occurs only for subsequent statements? I1 : R1+R2 – > R3 I2 : R3+ R1 –> R4 I3 : R3 + R4 → R4 isn’t I1 and I3 has RAW dependency.

asked Feb 2 in CO & Architecture by mehul vaidya (22 points) | 11 views

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Self doubt : Pipelining hazards
Assume a 5 stage pipeline with IF,ID,EX,MEM,WB stages.The number of RAW hazards in the given instruction sequence is? ADD R1,R2,R3 LD R2,0(R1) LD R1,4(R1) SUB R3,R1,R2

asked Feb 1 in CO & Architecture by vishal burnwal (135 points) | 67 views

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Self doubt-madeeasy que
Given the number of data pins as 64, indicates that word size of processor is 64 bit. And by default we consider memory as byte addressable i. E cell size shud be 8bit,but in madeeasy que they have given, #data pins 64 means memory cell size also 64bit but word size need not be equal to cell size. Then?? Plz clear this

asked Jan 30 in CO & Architecture by Adesh (6 points) | 12 views

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#Self_Doubt#DMA
Statement- During DMA transfer both the ‘CPU’ & “the program that requested DMA”, can continue their execution. Is this statement true or false & why ? Please give solution ASAP

asked Jan 29 in CO & Architecture by pass_i0n (15 points) | 13 views

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CO Ace test series : stack pointer

asked Jan 26 in CO & Architecture by Chirag Shilwant (180 points) | 23 views

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CO Question-11
Anyone please clarify if answer is 0.008 or 0.016?

asked Jan 25 in CO & Architecture by Shivateja MST (113 points) | 34 views

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Self Doubt: MADE EASY TLB
The virtual address generated by a CPU is $36 bits$, the Translation Look-aside Buffer (TLB) can hold $512$ $entries$ and a $8-way$ set associative, page size is $4 KB$ the size of the TLB tag is ________. Though I have solved the above ... ans $18$. But I have confusion regarding the above questions that I have asked. It will be very helpful if the reader can help.

asked Jan 24 in CO & Architecture by Debapaul (699 points) | 40 views

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COA Pipeline
I have a very basic doubt. Let us ignore the fact that we are executing this twice and focus on only executing it once. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S1 S1 S2 S3 S4 NOP S1 S2 S2 S2 S3 S3 S4 S4 NOP S1 S1 NOP S2 NOP S3 ... t place operations under a NOP, as that is tantamount to both stalling and executing in that particular cycle. If someone could clarify, that'd be of great help.

asked Jan 24 in CO & Architecture by goxul (377 points) | 16 views

+2 votes

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why there are no mantissa overflow in floating point multiplication?

asked Jan 24 in CO & Architecture by namekrakhnu (14 points) | 14 views

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Number of conflict and capacity miss
The answer should be 11, as there are 1 conflict and 1 capacity miss First conflict miss when 4 replaces 8 (even though there is an empty set 1 but it doesn't map to it so its a conflict miss), First capacity miss when at the end 3 replaces 5 as to if we had extra capacity then it wouldn't have been a miss. Am I right?

asked Jan 24 in CO & Architecture by Rishav_Bhatt (16 points) | 122 views

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Made easy test series : Pipelining stages
Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Consider the following ... on M-5. The number of the true statements(s) is/are ________. What will be the correct answer for above question?

asked Jan 23 in CO & Architecture by vishal burnwal (135 points) | 31 views

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Made Easy test series coa cache memory ft6
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4-way set associative LRU cache is used is ________. (Upto 1 decimal places) 100, 104, 108, 104, 107, 108, 105, 102, 108, 103

asked Jan 22 in CO & Architecture by Ram Swaroop (305 points) | 9 views

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CO Ace test series

asked Jan 21 in CO & Architecture by Chirag Shilwant (180 points) | 41 views

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Made Easy test series coa pipelining test5
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA), Write Back (WB) and their respective time requirements are 9 ns, 3 ns, 7 ns, 9 ns and 2 ns. Assume ... ________ (ns). I getting no of stall 90/4 = 22.5~=23 But in solution they take 22 So which is true ?

answered Jan 21 in CO & Architecture by shashin (1.9k points) | 34 views

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Ace test series : CO

asked Jan 21 in CO & Architecture by Chirag Shilwant (180 points) | 9 views

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Made Easy test series coa cache memory ft 3 cpi
Consider a CPU that executes at a clock rate of 200 MHz (5 ns per cycle) with a single level of cache. CPIexecution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% arithmetic/logical, 30% load/store, 20% control ... of 5 cycles. The number of times cpu with ideal memory is faster when no miss-occurs _______. (Upto 2 decimal places)

asked Jan 21 in CO & Architecture by Ram Swaroop (305 points) | 14 views

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madeeasy test series pipelining

asked Jan 21 in CO & Architecture by Dheeraj Varma (22 points) | 10 views

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1 answer

applied gate:cache
In solution they have taken data bit as 8 .i don’t understand how they get this?

answered Jan 21 in CO & Architecture by kalra05 (73 points) | 29 views

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Cache Question
Consider a single level cache with an access time of 6 ns, line size of 64 bytes and the hit ratio of 0.8. Main memory uses a block transfer capability that has a first word (8 bytes) access time of 40 ns and 15 ns for each word there after. ... cache miss? (Assume that the cache waits until the line has been fetched from main memory and re executes for a hit) Anyone please clarify.

asked Jan 21 in CO & Architecture by Shivateja MST (113 points) | 6 views

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Computer organization and architecture : Ace test series

answered Jan 19 in CO & Architecture by Pratyush Priyam Kuan (804 points) | 47 views

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Computer organization : Ace

asked Jan 19 in CO & Architecture by Chirag Shilwant (180 points) | 16 views

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Made easy test series : Pipelining concept
Consider the following 4-stages instruction pipeline where different instructions are spending different amount of time at different stages. Following loop is executed in the pipeline: How many cycles are required for above execution?

answered Jan 18 in CO & Architecture by neeraj_bhatt (275 points) | 42 views

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GATE MOCK TEST 3 GATE 2019 Q26 Cache
Here they did not ask for to which set 17th block will go to. Then it would have been 17 mod 2 = 1. Here they asked in which cache block it is present. I drew 4 cache lines (2 sets, each having 2 lines) and traced out the block requests and my final ... Line 0: 15 Set 1: Line 1: 17 ( so I called it the 4th line) Not sure what's the correct way to answer this.

asked Jan 18 in CO & Architecture by DukeThunders (415 points) | 10 views

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