Recent questions and answers in CO & Architecture - GATE CSE Doubts

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Computer organization and architecture : Ace test series

asked 1 hour ago in CO & Architecture by Chirag Shilwant (150 points) | 9 views

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Computer organization : Ace

asked 2 hours ago in CO & Architecture by Chirag Shilwant (150 points) | 6 views

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Made easy test series : Pipelining concept
Consider the following 4-stages instruction pipeline where different instructions are spending different amount of time at different stages. Following loop is executed in the pipeline: How many cycles are required for above execution?

answered 20 hours ago in CO & Architecture by neeraj_bhatt (235 points) | 18 views

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GATE MOCK TEST 3 GATE 2019 Q26 Cache
Here they did not ask for to which set 17th block will go to. Then it would have been 17 mod 2 = 1. Here they asked in which cache block it is present. I drew 4 cache lines (2 sets, each having 2 lines) and traced out the block requests and my final ... Line 0: 15 Set 1: Line 1: 17 ( so I called it the 4th line) Not sure what's the correct way to answer this.

asked 22 hours ago in CO & Architecture by DukeThunders (408 points) | 8 views

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COA GF TEST 2020

answered 2 days ago in CO & Architecture by shashin (1.2k points) | 36 views

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COA GF 2020 test

asked 2 days ago in CO & Architecture by Debapaul (615 points) | 22 views

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#ISRO#2020#CSE
STATEMENTS ASSOCIATED WITH REGISTERS OF A CPU ARE GIVEN. IDENTIFY THE FALSE STATEMENT (a) The program counter holds the memory address of the instruction in execution. (b) Only opcode is transferred to the control unit. (c) An instruction in the instruction ... (d) The value of the program counter is incremented by 1 once its value has been read to the memory address register.

answered 2 days ago in CO & Architecture by dr_Jackal (14 points) | 14 views

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Made Easy test series coa cache memory t2 16
Suppose that a processor has access to three levels of memory. Level 1 contain 2000 words and has an access time of 0.02 msec. Level 2 contain 10,000 words and has an access time of 0.2 msec. Level 3 contains 20,000 words and has an access time ... The hit ratio for level 1 is 0.65 and for level 2 is 0.45. The average access time (in μsec) is ________.

asked 2 days ago in CO & Architecture by Ram Swaroop (155 points) | 34 views

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Made Easy test series coa cache mapping single subject 33

asked 2 days ago in CO & Architecture by Ram Swaroop (155 points) | 18 views

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Average memory access time of cache
For this question, they've solved it using the formula AMAT = H1T1 + M1(H2T2 + M2 ...) and so on. However, since the question has directly given the hit time of the cache, I thought it'd be more appropriate to use the formula: ... ) + MissRate(MM)*(HitTime(Secondary))) So, which one is more appropriate and how would you differentiate between the two use cases?

asked 2 days ago in CO & Architecture by goxul (363 points) | 15 views

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Self doubt coa what is target address after if interrupt occurs after halt instructions

asked 3 days ago in CO & Architecture by Ram Swaroop (155 points) | 12 views

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Self doubt coa clock frequency
Memory cycle for immediate mode should be 0 is it correct? Consider 1GHz clock frequency processor,uses different operand accessing models shown below: Operand Accessing ModeFrequency(%) Register10 Immediate20 Direct30 Memory Indirect20 ... -series-co-%26-architecture-clock-frequency https://gateoverflow.in/25891/memory-addressing Please check above questions

asked 3 days ago in CO & Architecture by Ram Swaroop (155 points) | 8 views

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pipelining based
Consider a system with cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these are 50% of the total instructions. If the miss penalty is 30 clock cycles and the miss rate is 5%, how much ... the computer be if all instructions were cache hits? 1. 1 2. 2.8 3. 3.25 4. 4 can someone please explain this,

answered 3 days ago in CO & Architecture by shashin (1.2k points) | 17 views

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Made Easy test series coa cache memory access time

answered 3 days ago in CO & Architecture by tp21 (228 points) | 22 views

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ALU DATA PATH and FLOATING NUMBERS
Should I consider to put more efforts on ALU DATA PATH and FLOATING NUMBERS from COA in GATE 2020 as I am not getting those topics and not feeling so confident in these topics?

answered 3 days ago in CO & Architecture by Ram Swaroop (155 points) | 15 views

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applied gate grand test co

asked 3 days ago in CO & Architecture by abhinav649 (50 points) | 5 views

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applied gate co test
A full adder is implemented using XOR ,AND,OR gates.the propagation delay of AND and OR gates are half of XOR gates .and propagation delay of XOR gate is 2 ms.a 4 bit ripple carry adder is implemented using 4 full adders . The total propagation delay of 4 bit ripple carry adder will be____? Note:the input given to gates is not restricted to 2.the gates have fan-in more than 2.

asked 3 days ago in CO & Architecture by abhinav649 (50 points) | 7 views

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cache loading
In a two-level cache system, the access times of L1 and L2 are 4, 15 clock cycles respectively. The miss penalty from the L2 cache to main memory is 30 clock cycles. The miss rate of L1 cache is thrice that of L2. The average memory access time( ... the test series is very complicated and lengthy,is there any approach to solve it in a fast manner and get the concept in place right.

asked 4 days ago in CO & Architecture by Divyaok (20 points) | 13 views

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applied gate : co

asked 5 days ago in CO & Architecture by abhinav649 (50 points) | 7 views

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Made aesy test series : Data dependency
Consider the following sequence of assembly code: The number of data hazards in the above code are _______. What will be the correct answr for above question?

asked 5 days ago in CO & Architecture by vishal burnwal (117 points) | 9 views

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MADE EASY COA QUESTION
Consider a hypothetical control unit that supports 5 groups of mutually exclusive control signals. Also assume that group 1 & group 2 are using horizontal micro-programming whereas group-3, 4 and 5 are using vertical micro-programming. The total number of bits used for control words are ________. My doubt is what does it mean by 5 groups of mutually exclusive signals?

answered 6 days ago in CO & Architecture by shashin (1.2k points) | 26 views

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COA QUESTION
Consider the Main memory and cache memory having 4 word blocks. The cache is 20 times faster than main memory and its access time is 10nsec. Cache offers 80% hit for read operation and 90% hit for write operation. 40% of the reference represent the write ... has specified to do so? When to use write allocate and when to use write no allocate. Please clear. It's quite confusing

asked 6 days ago in CO & Architecture by RubyGATE (9 points) | 5 views

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ace test series computer organizations
Q. 7.

asked 6 days ago in CO & Architecture by Rahul Burman (19 points) | 12 views

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Made Easy Question

asked 6 days ago in CO & Architecture by RubyGATE (9 points) | 7 views

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Made Easy Cache memory
Consider the cache memory that is 30 times faster than main memory and used 90% of the total time. What is the speedup gain by the cache memory?

answered 6 days ago in CO & Architecture by shashin (1.2k points) | 23 views

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applied gate test series: hazards
consider following set of instructions. I1:ADD R1,R2,R1 I2:LW R2,0(R1) I3:LW R1,4(R1) I4:OR R3,R1,R2 the sum of (RAW ,WAR,WAW) dependencies in given instruction is: please explain why there is not any RAW hazard between I1 and I4

answered 6 days ago in CO & Architecture by shashin (1.2k points) | 9 views

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ME test series hazards
They are taking only adjacent onces, they haven't taken I1-I3 and I2-I4 RAW hazards. Someone kindly say what is the standard thing to follow concerning Gate. Should we take non-adjacent ones?

asked 6 days ago in CO & Architecture by sladewinter (7 points) | 15 views

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Online Test Series
Calculate the effective access time(in microseconds) of a two-level memory hierarchy system if the cache rate is 0.12, the miss penalty is 0.015 millisecond and cache memory access time is 10 microsecond.(Approximate to 1 decimal place)

asked Jan 10 in CO & Architecture by aseret (9 points) | 27 views

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Ace test Series Question-6
Anyone please clarify.

asked Jan 10 in CO & Architecture by Shivateja MST (96 points) | 34 views

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CO-ACE Academy
Instruction cycle is a combination of Fetch and Execution cycles. Consider the below instruction @ represents indirect addressing mode. MUL A,@5600 (Two word size) During the above instruction execution $5600$ acts as memory address.Minimum number of memory visits needed ... cycle is ___________ Ans given $4.$ How can I get this ? Any reference or chapter name for this question

asked Jan 9 in CO & Architecture by srestha (636 points) | 25 views

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Made Easy: Mock 1
“RAW hazards are taken only for consecutive statements?” Found this on https://gateoverflow.in/3622/gate2006-it-78

answered Jan 9 in CO & Architecture by shashin (1.2k points) | 45 views

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ACE Test Series Question-5
Can anyone please provide some valid explanation? I feel like only C to be correct.

asked Jan 9 in CO & Architecture by Shivateja MST (96 points) | 11 views

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GATE GURU: FLT 102
The amount of disk space that must be available for page storage is related to the maxi-mum number of processes,$N$, the number of bytes in the virtual address space, $V$ ,and the number of bytes of RAM, $R$. An expression for the worst-case disk-space requirements can be given as $NV$ $NV+R$ $NV-R$ $V$

answered Jan 7 in CO & Architecture by shashin (1.2k points) | 28 views

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ISRO QUESTION IN MADE EASY
An associative cache for a 64 K machine with 8 bit memory word is used. A block size of 4 is used,then cache memory word is in __________bits

asked Jan 7 in CO & Architecture by lokeshsharma123456 (9 points) | 23 views

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ACE Test Question-CO
A Dynamic RAM chip design includes with one refresh logic circuit one refresh operation refreshes only one row. In entire chip refresh period, some amount of time is used for refresh operation and remaining time is used for read/write operation. Let the size of DRAM is ... then calculated it But why we have to take $2^{20}$ number of rows?? It is not given in ques, right??

answered Jan 7 in CO & Architecture by priyesh9875 (59 points) | 35 views

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General Doubt-CO
value of “x over y” What is meaning of it?? $\frac{x}{y}$ or $\frac{y}{x}??$

asked Jan 6 in CO & Architecture by srestha (636 points) | 14 views

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Which Replacement algorithm works poorly in Block Replacement of an array, where elements are accessed in sequence.

asked Jan 6 in CO & Architecture by Pgoldar (6 points) | 15 views

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Doubt on interstage buffer delays
Consider a pipeline with 4 stages of delays 20,15,5,6.Let the buffer delay between each of the stages be 3ns,10ns,1ns,2ns respectively.What will be the cycle time of the clock? Is it 20+3 or 15+10? In other words should it be max(StageDelay) + Buffer delay or max(StageDelay + Buffer Delay)

asked Jan 6 in CO & Architecture by Aravind Adithya (7 points) | 11 views

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FULL SYLLABUS TEST-7 (ADVANCE LEVEL) GATE 2019 Q14 Dependency

asked Jan 5 in CO & Architecture by DukeThunders (408 points) | 14 views

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MadeEasyFULL SYLLABUS TEST-6 (ADVANCE LEVEL) GATE 2020 Q52

answered Jan 5 in CO & Architecture by shashin (1.2k points) | 25 views

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