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Recent questions and answers in Digital Logic
0
votes
1
answer
the gatebook ts
A certain JK FF has a propagation delay of 12ns. The largest MOD of the counter such that, the counter can be designed from these FFs which will operate up to 10 MHz?
answered
4 days
ago
in
Digital Logic
by
premu
(
69
points)

20
views
digitallogic
0
votes
0
answers
Made Easy timing Diagraam Q .51
I am very Confused in these types plsexplain in some detail.
asked
4 days
ago
in
Digital Logic
by
sridhar15399
(
9
points)

7
views
0
votes
1
answer
Made easy pls answer que no.11
answered
6 days
ago
in
Digital Logic
by
Saheb sarkar
(
9
points)

30
views
0
votes
1
answer
GATE19991.20 Video Solution
Booth's coding in $8$ bits for the decimal number $57$ is: $0100+1000$ $0100+1001$ $01+10010+1$ $0010+1001$
answered
Jun 25
in
Digital Logic
by
prajjwalsingh_11
(
16
points)

7
views
gate1999
digitallogic
numberrepresentation
boothsalgorithm
normal
videosolution
0
votes
0
answers
TestBook Test
In an SR latch by crosscoupling two NOR gates if S = 1 and R = 0, then, it’ll result in ___? Can anyone please explain the reason?
asked
Jun 22
in
Digital Logic
by
Jean
(
9
points)

17
views
testbooktestseries
digitallogic
#gatepreparation
0
votes
1
answer
GATE2004IT8 Video Solution
What is the minimum number of $\text{NAND}$ gates required to implement a $2\text{input EXCLUSIVEOR}$ function without using any other logic gate? $2$ $4$ $5$ $6$
answered
Jun 17
in
Digital Logic
by
Roshini
(
59
points)

9
views
gate2004it
digitallogic
minnogates
normal
videosolution
0
votes
1
answer
GATE2015343 Video Solution
The total number of prime implicants of the function $f(w, x, y, z) = \sum (0, 2, 4, 5, 6, 10)$ is __________
answered
Jun 17
in
Digital Logic
by
Roshini
(
59
points)

5
views
gate20153
digitallogic
canonicalnormalform
normal
numericalanswers
videosolution
0
votes
1
answer
GATE2017121 Video Solution
Consider the Karnaugh map given below, where $X$ represents "don't care" and blank represents $0$. Assume for all inputs $\left ( a,b,c,d \right )$ ... available. The above logic is implemented using $2$input $\text{NOR}$ gates only. The minimum number of gates required is ____________ .
answered
Jun 17
in
Digital Logic
by
Roshini
(
59
points)

3
views
gate20171
digitallogic
kmap
numericalanswers
normal
videosolution
0
votes
1
answer
GATE19992.16 Video Solution
The number of full and halfadders required to add $16$bit numbers is $8$ halfadders, $8$ fulladders $1$ halfadder, $15$ fulladders $16$ halfadders, $0$ fulladders $4$ halfadders, $12$ fulladders
answered
Jun 17
in
Digital Logic
by
Roshini
(
59
points)

4
views
gate1999
digitallogic
normal
adder
videosolution
0
votes
1
answer
GATE2015248 Video Solution
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is ... binary adder is implemented by using four full adders. The total propagation time of this 4bit binary adder in microseconds is ______.
answered
Jun 17
in
Digital Logic
by
Roshini
(
59
points)

10
views
gate20152
digitallogic
adder
normal
numericalanswers
videosolution
0
votes
0
answers
Chapter 2 Digital LogicTrishna GATE CSE&IT Excercise 1 Question 9
asked
Jun 10
in
Digital Logic
by
siddharths067
(
7
points)

15
views
#gatepreparation
#digital_electronics
0
votes
0
answers
MADE EASY TS
and gate or gate nor gate nand gate I think both option A and B are correct, because we need to reset at 110 and both Q1’ and Q2’ are 0 so both AND and OR will give same output. Can anyone confirm this.
asked
Jun 9
in
Digital Logic
by
ummokkate
(
64
points)

7
views
0
votes
0
answers
MADE EASY TS
I there are 13 flipflops used is PISO shift register circuit, then maximum number of clock cycles required to get the serial output is _____ ?
asked
Jun 9
in
Digital Logic
by
ummokkate
(
64
points)

9
views
digitallogic
madeeasytestseries
0
votes
0
answers
MADE EASY TS
The decimal value of the 2’s complement binary number 11101111110.0010 is ________? I got 130.125, but answer is something else.
asked
Jun 9
in
Digital Logic
by
ummokkate
(
64
points)

9
views
digitallogic
madeeasytestseries
0
votes
1
answer
MADE EASY TS
A function f(x,y,z) = x XNOR y XNOR z = 1, then which of the following is always true? x + yz =1 x not equal to (y XOR z) x.y.z =1 x = y XNOR z I’m getting both option b and option d.
answered
Jun 8
in
Digital Logic
by
Rudr Pawan
(
788
points)

22
views
madeeasytestseries
digitallogic
0
votes
0
answers
MADE EASY TS
Here my doubt is that when we get the equation of y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3, given I0, I3 are S1 and I1, I2 are S0 so when we will substitute them, will be substitute y = S1’S0’S1 + S1’S0S0 + S1S0’IS0+ S1S0S1 or will we substitute y = S1’S0’S1’ + S1’S0S0 + S1S0’S0’+ S1S0S1 according to the value of select lines. I’m a bit confused.
asked
Jun 8
in
Digital Logic
by
ummokkate
(
64
points)

12
views
digitallogic
madeeasytestseries
0
votes
0
answers
THE GATEBOOK TS
Consider the boolean function that has the don't care states: and . How many prime implicants (P) and essential prime implicants (EP) are there for F? (A). Five (P) and Three (EP) (B). Four (P) and Three (EP) (C). Five (P) and Two (EP) (D). Six ... Three (EP) I'm getting option B, but answer given is option A. Reason given is don't cares will also make 1 PI, can anyone confirm it.
asked
Jun 7
in
Digital Logic
by
ummokkate
(
64
points)

10
views
digitallogic
kmap
+2
votes
0
answers
Self doubt on GB: Digital Logic
When two 8bit numbers and in 2's complement representation (with and as the least significant bits) are subtracted(i.e. AB) by first negating the subtrahend and then adding it to the minuend using a ripplecarry adder, the sum bits obtained are and the carry ... 1 (B). is 1 (C). is 1 (D). is 1 How this question will differ from previous GATE question? Plz verify
asked
Jun 1
in
Digital Logic
by
srestha
(
749
points)

18
views
digitallogic
0
votes
0
answers
What is sum term in kmap?
asked
May 23
in
Digital Logic
by
Rashimdixit
(
7
points)

8
views
0
votes
0
answers
Is algebraically complete and functionally complete the same thing?
asked
May 23
in
Digital Logic
by
Rashimdixit
(
7
points)

3
views
0
votes
0
answers
Seven segment led display
asked
May 17
in
Digital Logic
by
Ashish Thakor
(
7
points)

7
views
output
0
votes
0
answers
SELF DOUBT(DIGITAL)
https://gateoverflow.in/120055/isro2009ecemodcounter FOR THIS QUEESTION WHY ARE WE ONLY CONSIDEREING THE RIPPLE COUNTER AND NOT CONSIDERING THE SYNCHRONOUS COUNTERS?
asked
May 10
in
Digital Logic
by
Doraemon
(
115
points)

8
views
+1
vote
1
answer
GATE2020CS28 Video Solution
Consider the Boolean function $z(a,b,c)$. Which one of the following minterm lists represents the circuit given above? $z=\sum (0,1,3,7)$ $z=\sum (1,4,5,6,7)$ $z=\sum (2,4,5,6,7)$ $z=\sum (2,3,5)$
answered
Apr 30
in
Digital Logic
by
amitkhurana512
(
187
points)

8
views
gate2020cs
digitallogic
videosolution
+1
vote
1
answer
GATE2020CS19 Video Solution
A multiplexer is placed between a group of $32$ registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is ______.
answered
Apr 29
in
Digital Logic
by
amitkhurana512
(
187
points)

19
views
gate2020cs
numericalanswers
digitallogic
videosolution
0
votes
0
answers
How we got exponent as $2^{12764}$?
Information: Consider a 16bit register of the following format is used to store a floating point number. Mantissa (M) is denoted as normalized signed magnitude fraction, Exponent (E) is expressed in excess64 form. Base of the system is ... ? Please explain it as you are explaining to naive person. I am missing something very obvious! Waiting for explanation!
asked
Apr 24
in
Digital Logic
by
ubibhatt
(
6
points)

7
views
floating_point
digitallogic
+1
vote
1
answer
GATE2020CS20 Video Solution
If there are $m$ input lines $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .
answered
Apr 23
in
Digital Logic
by
amitkhurana512
(
187
points)

12
views
gate2020cs
numericalanswers
digitallogic
videosolution
0
votes
0
answers
GATE19891vi
It would be helpful if you provide me the solution. i'm not able to understand the solution which is given in go site. please provide me detailed explanation GATE19891vi Consider an excess  50 representation for floating point ... digit exponent in normalised form. The minimum and maximum positive numbers that can be represented are __________ and _____________ respectively.
asked
Apr 20
in
Digital Logic
by
varunraj
(
9
points)

7
views
numberrepresentation
digitallogic
floatingpointrepresentation
0
votes
0
answers
GATE199202ii
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: All digital circuits can be realized using only A.ExOR gates B.Multiplexers C.Half adders D.OR gates I have a doubt in question ... complete or partially functionally complete? multiplexer and Half adders are partially functionally complete.WHAT IS THE ACTUAL ANSWER??????
asked
Apr 19
in
Digital Logic
by
varunraj
(
9
points)

4
views
functionalcompleteness
digitallogic
adder
multiplexer
0
votes
0
answers
GATE20068 digital logic
please explain me the solution and how to draw timing diagrams for this kind of questions?
asked
Apr 19
in
Digital Logic
by
varunraj
(
9
points)

4
views
digitallogic
flipflop
#frequency
clocktime
clockfrequency
0
votes
0
answers
Decoder and free variables
Why do we minimize the output of decoder to calculate free variables?
asked
Apr 19
in
Digital Logic
by
bhardwaj.aakash_420
(
10
points)

2
views
0
votes
1
answer
GATE2016208 Video Solution
Let, $x_{1} ⊕ x_{2} ⊕ x_{3} ⊕ x_{4}= 0$ where $x_{1}, x_{2}, x_{3}, x_{4}$ are Boolean variables, and $⊕$ is the XOR operator. Which one of the following must always be TRUE? $x_{1}x_{2}x_{3}x_{4} = 0$ $x_{1}x_{3} + x_{2} = 0$ $\bar{x}_{1} ⊕ \bar{x}_{3} = \bar{x}_{2} ⊕ \bar{x}_{4}$ $x_{1} + x_{2} + x_{3} + x_{4} = 0$
answered
Apr 19
in
Digital Logic
by
bhardwaj.aakash_420
(
10
points)

11
views
gate20162
digitallogic
booleanalgebra
normal
videosolution
0
votes
0
answers
GATE201618 Video Solution
We want to design a synchronous counter that counts the sequence $010203$ and then repeats. The minimum number of $\text{JK}$ flipflops required to implement this counter is _____________.
asked
Apr 19
in
Digital Logic
by
admin
(
3.6k
points)

6
views
gate20161
digitallogic
digitalcounter
flipflop
normal
numericalanswers
videosolution
0
votes
0
answers
GATE201527 Video Solution
The minimum number of JK flipflops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is _______.
asked
Apr 19
in
Digital Logic
by
admin
(
3.6k
points)

3
views
gate20152
digitallogic
digitalcounter
normal
numericalanswers
videosolution
0
votes
0
answers
GATE2016133 Video Solution
Consider a carry look ahead adder for adding two nbit integers, built using gates of fanin at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
asked
Apr 19
in
Digital Logic
by
admin
(
3.6k
points)

1
view
gate20161
digitallogic
adder
normal
videosolution
0
votes
0
answers
GATE200462 Video Solution
A 4bit carry look ahead adder, which adds two 4bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time ... the carry network has been implemented using twolevel ANDOR logic. 4 time units 6 time units 10 time units 12 time units
asked
Apr 19
in
Digital Logic
by
admin
(
3.6k
points)

3
views
gate2004
digitallogic
normal
adder
videosolution
0
votes
0
answers
GATE200734 Video Solution
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n1}$ line to $1$line $2^{n2}$ line to $1$line
asked
Apr 19
in
Digital Logic
by
admin
(
3.6k
points)

1
view
gate2007
digitallogic
normal
multiplexer
videosolution
0
votes
0
answers
GATE200638 Video Solution
Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $ i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle $ ... $ wx\overline{y} \overline{z}, xz, w\overline{x}yz$ $ wx\overline{y}, wyz, wxz, \overline{w}xz, x\overline{y}z, xyz$
asked
Apr 19
in
Digital Logic
by
admin
(
3.6k
points)

2
views
gate2006
digitallogic
minsumofproductsform
difficult
statichazard
videosolution
0
votes
0
answers
GATE201032 Video Solution
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$ $10$, $11$, $01$, $00$ $10$, $00$, $01$, $11$ $11$, $10$, $00$, $01$
asked
Apr 19
in
Digital Logic
by
admin
(
3.6k
points)

1
view
gate2010
digitallogic
circuitoutput
normal
videosolution
0
votes
0
answers
GATE2017212 Video Solution
Given the following binary number in $32$bit (single precision) $IEEE754$ format : $\large 00111110011011010000000000000000$ The decimal value closest to this floatingpoint number is : $1.45*10^1$ $1.45*10^{1}$ $2.27*10^{1}$ $2.27*10^1$
asked
Apr 19
in
Digital Logic
by
admin
(
3.6k
points)

1
view
gate20172
digitallogic
numberrepresentation
floatingpointrepresentation
ieeerepresentation
videosolution
0
votes
0
answers
GATE20078, ISRO201131 Video Solution
How many $3$to$8$ line decoders with an enable input are needed to construct a $6$to$64$ line decoder without using any other logic gates? $7$ $8$ $9$ $10$
asked
Apr 19
in
Digital Logic
by
admin
(
3.6k
points)

1
view
gate2007
digitallogic
normal
isro2011
decoder
videosolution
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