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Recent questions and answers in Digital Logic
0
votes
0
answers
GATE ECE PREVIOUS YEAR QUESTIONS BOOK
asked
Mar 6
in
Digital Logic
by
Atulvstar
(
5
points)

14
views
selfdoubt
+1
vote
0
answers
TIFR 2020 Question 1 Computer Science section
Consider the following Boolean valued function on n Boolean variables: f(x1, ,xn)=x1+⋯+xn(mod 2), where addition is over integers, mapping FALSE' to 0 and TRUE' to 1. Consider Boolean circuits (with no feedback) that use only logical AND and OR gates, and ... 2^o(logn) n^c, for some fixed constant c n^ω(1), but n^O(logn) 2^Θ(n) None of the others
asked
Feb 28
in
Digital Logic
by
harleenkaur
(
9
points)

24
views
selfdoubt
0
votes
0
answers
while solving a flip flop question i came around this situation.
asked
Feb 12
in
Digital Logic
by
Arpit Somani
(
5
points)

23
views
selfdoubt
0
votes
1
answer
Made easy test
Explain me this question with boolean function form.(not k map)
answered
Feb 5
in
Digital Logic
by
shantanu4raje
(
25
points)

26
views
digitallogic
0
votes
0
answers
Made easy test
Explain me this question.
asked
Feb 5
in
Digital Logic
by
Enolx.21
(
49
points)

16
views
digitallogic
0
votes
1
answer
Made Easy Workbook
How can we minimize this function? Ans(d)
answered
Feb 2
in
Digital Logic
by
zxy123
(
3.6k
points)

37
views
digitallogic
+1
vote
0
answers
Self Doubt: Digital logic design
This question is from GATE 2019 Instrumentation branch (Digital logic) Can anyone solve this and can explain what is meant by steady state? Ans: 4
asked
Jan 23
in
Digital Logic
by
phaneendrababu
(
11
points)

39
views
digitallogic
+1
vote
1
answer
GATE CSE 2004
Let A=1111 10101010 and B=0000 10101010 be two 8bit 2′s complement numbers. Their product in 2′s complement is
answered
Jan 23
in
Digital Logic
by
SarathBaswa
(
849
points)

25
views
numbersystem
0
votes
1
answer
GATE CSE 2018
Consider the unsigned 8bit fixed point binary number representation below b7 b6 b5 b4 b3 . b2 b1 b0 where the position of the binary point is between b3 and b2. Assume b7 is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation: (i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001
answered
Jan 22
in
Digital Logic
by
Abhisheksmile94
(
347
points)

14
views
numbersystem
+1
vote
1
answer
Tga test series
answered
Jan 12
in
Digital Logic
by
zxy123
(
3.6k
points)

18
views
selfdoubt
0
votes
0
answers
Tga mock test
MSQ Type question.
asked
Jan 11
in
Digital Logic
by
Enolx.21
(
49
points)

19
views
selfdoubt
0
votes
0
answers
Made Easy Testseries Digital Q4
A flipflop has 3 ns delay from the time the clock edge occurs to the time the output is complemented. What is the maximum frequency at which mod1024 counter can operate reliably? 33 MHz 40 MHz 33.3 MHz 10 MHz
asked
Jan 5
in
Digital Logic
by
Shivateja MST
(
45
points)

48
views
digitallogic
0
votes
0
answers
#testquestion
#digital ckts number system GRE QUESTION Given ans is D... Post the detailed solution
asked
Dec 29, 2020
in
Digital Logic
by
Amit puri
(
5
points)

76
views
number
numbersystem
0
votes
1
answer
Applied Ai Test Series
2’s complement representation for (12121) base 3 ? 10010111 base 2 01011011 base 2 01011111 base 2 01011010 base 2
answered
Dec 22, 2020
in
Digital Logic
by
Deepakk Poonia (Dee)
(
1.5k
points)

19
views
digitallogic
0
votes
0
answers
Unacademy test series Digital Q2
Odd function B. Even Function C. Identity function D. Both B and C
asked
Dec 19, 2020
in
Digital Logic
by
Shivateja MST
(
45
points)

18
views
digitallogic
0
votes
1
answer
Unacademy Digital Quesn 1
A 1bit full adder takes 20ns to generate a carryout bit and takes 40ns to generate a sum bit. The maximum rate of addition per second when four 1bit full adder are cascaded is _______ x 10^7. Anyone please clarify.
answered
Dec 18, 2020
in
Digital Logic
by
Sahil91
(
683
points)

47
views
digitallogic
0
votes
1
answer
Self doubt  digital logic
Kmap 0 1 0 0 0 1 X 0 0 X X 0 0 0 0 0 X= don’t care Derive the minimum SumofProduct form for this.
answered
Dec 17, 2020
in
Digital Logic
by
gajendercse
(
41
points)

22
views
selfdoubt
digitallogic
0
votes
0
answers
4bit synchronous updown counter designed using a Tflip flow.
asked
Dec 16, 2020
in
Digital Logic
by
junpyo
(
5
points)

12
views
digitallogic
0
votes
0
answers
Made easy Digital Logic Q1
Anyone please clarify. I feel answer to be 16 ms.
asked
Dec 15, 2020
in
Digital Logic
by
Shivateja MST
(
45
points)

48
views
digitallogic
counters
0
votes
0
answers
Question taken from book morris mano 3rd edition chapter 3 question number 26
asked
Dec 14, 2020
in
Digital Logic
by
fahad137
(
5
points)

14
views
digitallogic
0
votes
1
answer
#selfdoubt #logicdesign
IN excess 3 code The binary sum of a code and its 9′s complement is equal to 9. can someone explains meaning of this statement with example.
answered
Dec 7, 2020
in
Digital Logic
by
Sahil91
(
683
points)

24
views
digitallogic
0
votes
0
answers
Made Easy test series
How to know through representation which one is LSB and which one is MSB
asked
Dec 3, 2020
in
Digital Logic
by
vimal12
(
5
points)

21
views
testseries
digitallogic
0
votes
1
answer
Made Easy TextBook Assignments Counters #self doubt
answered
Dec 2, 2020
in
Digital Logic
by
zxy123
(
3.6k
points)

24
views
counters
digitallogic
+2
votes
1
answer
NLCIL2020(PSU)
Q.1) what is minimum number of NAND gate require to implement the function$A^{'}C^{'}+B^{'}C^{'}+CD$.there is only 2input NAND gate available.
answered
Nov 30, 2020
in
Digital Logic
by
_sajalrai_
(
569
points)

42
views
psu
0
votes
0
answers
Made Easy Text Book Counters 2018 Delay of ripple counter and synchronous counter
asked
Nov 30, 2020
in
Digital Logic
by
ayusha5312
(
21
points)

13
views
digitallogic
0
votes
0
answers
Made Easy Text Book Counters 2018 Delay of ripple counter and synchronous counter
asked
Nov 30, 2020
in
Digital Logic
by
ayusha5312
(
21
points)

17
views
digitallogic
+3
votes
1
answer
Gateoverflow test series question.
Assume that the propagation delay in each gate in a 16bit ripple carry adder (made of AND, OR, and NOT gates only with up to 3 inputs) is 1 ns. Time taken in nanoseconds to perform a 16bit addition is _______. Given answer is 33 nanoseconds. How to solve this question?
answered
Nov 29, 2020
in
Digital Logic
by
_sajalrai_
(
569
points)

90
views
digitallogic
0
votes
0
answers
Made Easy TextBook Counters Gate CS .#Self Doubt
Please provide detailed solution.
asked
Nov 29, 2020
in
Digital Logic
by
ayusha5312
(
21
points)

33
views
digitallogic
counters
0
votes
0
answers
NIC STA 2020 SET A 54
Q. How many AND, OR and XOR gate are required for implementation of full adder? A) 1,2,2 B) 2,2,1 C) 3,2,2 D) 3,0,1 I think none of the option match Plz check
asked
Nov 27, 2020
in
Digital Logic
by
Hradesh patel
(
9
points)

15
views
digitallogic
0
votes
0
answers
NiC STA 2020 set A 111
Q. Encoder are made by three.......gates. A) AND B) OR C) NAND D) XOR I think question framing wrong Plz check
asked
Nov 27, 2020
in
Digital Logic
by
Hradesh patel
(
9
points)

18
views
digitallogic
0
votes
1
answer
Made Easy Sequential Circuits 2018 #self doubt
Please provide the detailed solution!
answered
Nov 26, 2020
in
Digital Logic
by
zxy123
(
3.6k
points)

19
views
digitallogic
0
votes
0
answers
NIELIT NIC STA 2020 setC ques 100
Which flip flop is used to make all type of shift registers? JK flipflop D flipflop T flipflop all options using D we can obviously make all shift registers but cant we use JK or any other flip flop to do so?
asked
Nov 26, 2020
in
Digital Logic
by
ayush.5
(
99
points)

23
views
shiftregisters
0
votes
1
answer
NIELIT NIC scientistB 2020 setC ques 51
X Y X$Y 1 0 1 1 1 1 0 1 0 0 0 1 Identify the matching boolean expression. X$~Y ~X$Y ~X$~Y none of the options
answered
Nov 26, 2020
in
Digital Logic
by
zxy123
(
3.6k
points)

21
views
booleanalgebra
+1
vote
1
answer
Made Easy Text Book Sequential Circuit #2018 #JK Flip Flops
answered
Nov 25, 2020
in
Digital Logic
by
zxy123
(
3.6k
points)

19
views
digitallogic
0
votes
1
answer
Made Easy Test Series, Digital Logic , Combinational Circuits
answered
Nov 24, 2020
in
Digital Logic
by
ayusha5312
(
21
points)

61
views
digitallogic
+1
vote
1
answer
MadeEasy textbook Digital logic combinational circuits
answered
Nov 23, 2020
in
Digital Logic
by
zxy123
(
3.6k
points)

24
views
digitallogic
0
votes
1
answer
MadeEasy text book Digital logic Combinational circuits 2018
answered
Nov 23, 2020
in
Digital Logic
by
zxy123
(
3.6k
points)

27
views
digitallogic
0
votes
0
answers
Made Easy test Series
F is a boolean function in 4 boolean variables x,y,z, and w. $F(x,y,z,w) = \sum \left ( 0,1,4,11,12,13,15 \right )$ Then the expression for the dual of F is: Solution: I could not understand the 2nd line, If $F$ is $0$ for term $x$ ... I could not understand, why would $(2^4 1 x)$ be a minterm of $F^d$. Please if someone could explain would be of great help. Thanks!
asked
Nov 22, 2020
in
Digital Logic
by
Sarrthak
(
5
points)

23
views
madeeasytest
booleanalgebra
0
votes
0
answers
Sequential Circuit
Draw the sequential circuit for serial adder using shift registers, full adder and DFF. Explain its operation with state equations and state table .
asked
Nov 19, 2020
in
Digital Logic
by
Asad5059
(
5
points)

16
views
digitallogic
0
votes
0
answers
Will Download B.S. Grewals in Higher Mathematics bring antivirus？
asked
Nov 18, 2020
in
Digital Logic
by
Ellalucky
(
5
points)

15
views
selfdoubt
digitallogic
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