Recent questions and answers in Digital Logic - GATE CSE Doubts

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MADEEASY DLD
OR NAND XOR AND How to approach such questions. Kindly provide the detailed explanation.

asked 1 day ago in Digital Logic by Rudr Pawan (688 points) | 9 views

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Self doubt in digital logic
https://gateoverflow.in/233283/pi-and-epi-in-case-of-dont-care?show=328136#c328136 In that question answer explains that all x's(don't care terms) can be combined to form a prime implicant. But my doubt is that even if any ... group occurs functions value may not be true. Because by definition implicant is that whose truthness implies truthness of function. Thanks.

asked 1 day ago in Digital Logic by Vimal Patel (341 points) | 3 views

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MOCK EXAM ACE
Consider the following statements regarding counters: S1 : The Hamming distance of an Overbeck counter is 1 and the Hamming distance of a Johnson counter is 2. S2 : Only output sequence 0, 8, 12, 14, 15, 7, 3, 1, 0, ... is possible in Overbeck counter but not output sequence 2, ... S2, S3 are false and S1 is true (C) Only S1, S3 are false and S2 is true (D) All S1, S2, and S3 are true

asked 6 days ago in Digital Logic by Dipanshu Rana (24 points) | 18 views

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Made easy test series: sequential circuit
Answer is given as 33.33 MHz. But my doubt is that they have considered only NAND gates and not flip flops which will give mod 4 counter, due to which answer should be 33.33 / 4 = 8.33 MHz Am i right or wrong?

asked 6 days ago in Digital Logic by vishal burnwal (45 points) | 5 views

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Made easy practice questions book

asked 6 days ago in Digital Logic by Jyoti Kumari97 (18 points) | 13 views

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Made-easy-booklet

asked 6 days ago in Digital Logic by Jyoti Kumari97 (18 points) | 6 views

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Made easy practice questions book 2019

asked 6 days ago in Digital Logic by Jyoti Kumari97 (18 points) | 6 views

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Self Doubt - MUX
$1)$ If we want to implement $n$ variable function with $2^{n}\times 1$ MUX, is it possible? $2)$ If we want to implement $n$ variable function with $2^{n}\times 1$ MUX and with NOT gate, is it possible? Someone plz xplain which one possible and which one not possible, and why??

answered Nov 30 in Digital Logic by Priyansh Singh (118 points) | 19 views

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ACE-Digital Counter
A cascaded arrangement of Flip-Flops, where the output of one flipflop drives the clock input of the following FlipFlop, is known as $A)$ Synchronous Counter $B)$ Ripple Conter Is it Asynchronous counter? But I have seen this line, which says ripple ... output is free from the clock signal. Plz tell me, where am I going wrong? https://www.electronicshub.org/asynchronous-counter/

asked Nov 29 in Digital Logic by srestha (522 points) | 13 views

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Applied course test series: Combinational circuits

asked Nov 28 in Digital Logic by vishal burnwal (45 points) | 11 views

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Applied course test series : Logic gates
Please provide the answer and explaination for the above question.

answered Nov 28 in Digital Logic by Satbir (3.7k points) | 11 views

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Self Doubt-GATE question
Please check this ques https://gateoverflow.in/1057/gate2004-62 How it could be done in 6 unit time? I think EXOR gate itself need 4 NAND gate. So, And 3 NAND gate is required. Isnot it? Now, 3 AND gate and 2 OR gate required to complete the circuit. Isnot it?

asked Nov 27 in Digital Logic by srestha (522 points) | 17 views

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ACE Test Series CSIT_P_39 Q7: Calculating ROM size

asked Nov 26 in Digital Logic by DukeThunders (288 points) | 21 views

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ACE Test Series CSIT_P_39 Q10: Race Around Condition

asked Nov 26 in Digital Logic by DukeThunders (288 points) | 9 views

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2 answers

ACE-Comparator circuit
If $A$ and $B$ $4$ bit binary numbers given to a $4$ bit comparator, Then the number of combination $A>B$ is_________ Ans given $120,$ but how is it possible? Again they done with a formula. But with K-Map, I got only 6. Which one correct?

answered Nov 26 in Digital Logic by Shaik Masthan (485 points) | 35 views

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Digital:ACE Test
To design $7\times 128$ decoder, minimum number of $2\times 4$ decoder required is ___________? My ans $147$, while given ans $43,$ Which one correct?

answered Nov 26 in Digital Logic by Satbir (3.7k points) | 30 views

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ACE-NAND GATEs
To design $16$ input NAND gate, the number of $2$ input NAND gate required is ______________ Ans given 29,with a formula 2n-3, but why? I think last level required 8 NAND gate 2nd level required 4 NAND gates Similarly 3rd level 2 and 4th level 1 NAND gates, so, total 15 NAND gates. Where Am I going wrong?

answered Nov 26 in Digital Logic by toxicdesire (170 points) | 16 views

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ACE Test:Digital
A $1$ bit full adder takes $20$ns. to generate carry out bit and $40$ns. to the sum bit. When four $1$bit full adder is cascaded, then the total time for addition is __________ ns. They used this formula N-bit parallel adder time for addition=$\left ( N-1 \right )t_{c}+ Max(t_{s},t_{c})$ Is this a correct formula? What should be ans??

asked Nov 25 in Digital Logic by srestha (522 points) | 30 views

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Digitallogic question
How many no of ternary functions are possible with 2 boolean variables? Is this correct logically? I mean with 2 boolean variables we can have functions of just 2 variables at maximum right? Anyone please clarify.

answered Nov 24 in Digital Logic by GAITONDE (1.6k points) | 36 views

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ACE Test-Digital
In the double precession IEEE standard exponent value in decimal is $2047.$ and significant value in decimal is $‘0’ $ The above value represent Implicit number $\left ( -1 \right )^{s}0$ $\left ( -1 \right )^{s}\alpha$ NAN

asked Nov 23 in Digital Logic by srestha (522 points) | 14 views

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Digital GATE1993-6.2 Question Doubt.
Source – https://gateoverflow.in/17235/gate1993-6-2 Can someone please explain this question. I am not getting the explanation provided. Thanks!

answered Nov 23 in Digital Logic by Satbir (3.7k points) | 19 views

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Self doubt : In boolean expression simplification
suppose we have something like this: f1(p,q,r) = minterms(1,3,7) f2(p,q,r) = minterms(0,3,6) F = minterms( f1’.f2’ ) = minterms( (1,3,7)’.(0,3,6)’ ) How we simplify this F function directly?

answered Nov 22 in Digital Logic by pranay562 (666 points) | 19 views

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self doubt: Multiplexer are functionally complete or partially functionally complete

asked Nov 21 in Digital Logic by shaktisingh (85 points) | 18 views

+1 vote

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Self Doubt: r's complement
Is this ans correct? https://gateoverflow.in/235417/ace-test-series-digital-logic-number-system We know that 7's complement of a number is $7777 .- x$ , where x can be any number. And for 8's complement we need to add $1$ with it. Means for ... add 1, Isnot it? Then how in this question ,we are subtracting directly from 8888, which is an even number? Plz someone tell me.

asked Nov 21 in Digital Logic by srestha (522 points) | 14 views

+1 vote

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Success gateway test series
$f_{1}(A,B,C,D)=\Sigma m(0,1,8,9)+\Sigma d(2,10,15)$ $f_{2}(A,B,C,D)=\Sigma m(0,2,9,14)+\Sigma d(1,8,15)$ What is $f_{1}+f_{2}$ and $f_{1}.f_{2}$

answered Nov 21 in Digital Logic by Satbir (3.7k points) | 53 views

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floating point representation
How to represent 5.5 decimal no in the IEEE 754(single precision format) using normal bias and with and without using normalization.

asked Nov 18 in Digital Logic by ankitron (7 points) | 8 views

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1 answer

#test series 2019
Explain clean way

answered Nov 18 in Digital Logic by pranay562 (666 points) | 18 views

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UEMK GATE MOCK :DIGITAL
What will be the ans , and how to approach?

asked Nov 16 in Digital Logic by Debapaul (308 points) | 15 views

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asked Nov 16 in Digital Logic by Debapaul (308 points) | 8 views

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Self doubts dld
$F(a,b,c)=F(\bar{a},\bar{b},\bar{c})$ no function possible

asked Nov 13 in Digital Logic by amit166 (112 points) | 12 views

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#Digital Ripple Carry Adder Delay Numerical.
Source - https://www.gatevidyalay.com/delay-in-ripple-carry-adder/ Following figure shows the implementation of full adders in a 16-bit ripple carry adder realized using 16 identical full adders. The propagation delay of the XOR, AND and OR gates are 20 ns, 15 ns ... case delay of this 16 bit adder will be ______? A) 395 ns B) 220 ns C) 400 ns D) 300 ns

answered Nov 9 in Digital Logic by GAITONDE (1.6k points) | 11 views

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#DLD How to find delay in Carry look ahead adder?
Ques 1) Exclusive−OR gate has a propagation delay of 10 ns and that the AND or OR gates have a propagation delay of 5 ns.What is the total propagation delay time in the four-bit adder.Assume FAN−IN=2 1) ripple adder 2) ... -ripple-carry Ques 2) https://gateoverflow.in/80674/can-anybody-explain-carry-look-ahead-delay-delay-and-and-and Thank you!

asked Nov 9 in Digital Logic by iarnav (76 points) | 6 views

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MEMORY-ORGANISATION( RAM / ROM CHIP PROBLEMS
I couldn't find any good source of problems on ramr chips,no. of decoders,size of decoders, etc If anyone got any such memory organisation chip related maths, theory explained pdf links, example workout links, etc please share. please don't flag this thread as invalid or something.. Chip related all problems are hard to find in 1 place.

asked Nov 9 in Digital Logic by blackcloud (7 points) | 13 views

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answered Nov 8 in Digital Logic by pranay562 (666 points) | 12 views

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MadeEasy DIGITAL LOGIC-2 (GATE - 2019) Q17
Here when S=R=1, how to decide whether it should set or hold? T is given as 0 for both the cases. Same goes for S=R=0, will it hold or reset?

asked Nov 6 in Digital Logic by DukeThunders (288 points) | 22 views

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MadeEasy DIGITAL LOGIC-1 (GATE - 2020) Q17
How to solve this

asked Nov 6 in Digital Logic by DukeThunders (288 points) | 19 views

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MadeEasy DIGITAL LOGIC-1 (GATE - 2019) Q17

asked Nov 6 in Digital Logic by DukeThunders (288 points) | 35 views

+2 votes

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GATE GURU 2020: DLD
Minimum number of NOR gates required to implement (A+B+C)’ is_______________ . 4 3 2 5 How to approach these types of question, I always do mistakes in these

answered Nov 4 in Digital Logic by pranay562 (666 points) | 47 views

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GATE CSE GATE Guru:DIGTAL
Consider the function f(a,b,c) = Ʃ(1,3,5,7) + ϕ(0,4). To find the minimal expression for the function f , the don’t cares are treated as 1. 4 is minterm and 0 maxterm 2. Both are maxterms 3. 0 is minterm and 4 maxterm 4. Both are minterms

asked Nov 4 in Digital Logic by Debapaul (308 points) | 19 views

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1 answer

GATE FORUM: DIGITAL LOGIC
Ans should be $10$ right?

answered Nov 3 in Digital Logic by Rudr Pawan (688 points) | 29 views

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