Recent questions and answers in Digital Logic
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Recent questions and answers in Digital Logic

Recent questions and answers in Digital Logic
0 votes
0 answers 29 views
Topic : Digital Logic - Adders
I am very much confused while solving the questions involving adder circuits like Half Adder, Full Adder, Ripple Carry Adder, Carry Look Ahead Adder, etc. I can solve none of the questions, and leave almost all questions involving them. My concept ... me some good source from where I can learn them and practice questions on them. It would be really helpful for me.
Abhrajyoti00 asked in Digital Logic Sep 5
by Abhrajyoti00
5 points
29 views
0 votes
0 answers 38 views
Trishna Knowledge Systems. GATE Computer Science and Information Technology , Chapter - Digital Electronics ,Unit-1 ,
Bishes asked in Digital Logic Sep 2
by Bishes
5 points
38 views
0 votes
0 answers 29 views
Introduction to logic circuits and logic design using VHDL, chapter combinational logic design, pg-111.
Noob coder asked in Digital Logic Sep 2
by Noob coder
5 points
29 views
0 votes
0 answers 33 views
Is there any specific benefit of using Prime Implicant table in finding minimal SOP for cyclic functions?
RanajitRoy asked in Digital Logic Aug 24
by RanajitRoy
5 points
33 views
0 votes
0 answers 22 views
Self Doubt about XOR being linear
Why is xor a linear function as specified on multiple online sources? 01 → 11 is decreasing and 10 → 11 is also decreasing. Shouldn't it be non linear. I want to prove why {XOR, NOT} are not functionally complete.
aryavart asked in Digital Logic Aug 24
by aryavart
73 points
22 views
0 votes
0 answers 35 views
made easy test series
if F is a bool. functio in four variable x.y,z,w f(x,y,z,w)= sum (0,1,4,11,12,13,15) then expension for dual of f is…………..
jugnu1337 asked in Digital Logic Aug 23
by jugnu1337
5 points
35 views
0 votes
0 answers 31 views
Sequential Circuits (Digital Logic)
Are Synchronous Circuits easy to implement than Asynchronous Circuits OR the opposite? I have seen varying answers on the internet so this got me confused. Any explanation would help.
Rahul Aryan asked in Digital Logic Aug 20
by Rahul Aryan
5 points
31 views
0 votes
0 answers 23 views
KSET 2015 COMPUTER SCIENCE AND APPLICATION
Consider a combinational circuit designed using ROM that accepts a 3-bit number and generates an output binary number equal to the square of the input number.What is minimum size of the ROM ? (A)3 × 4 (B)3 × 8 (C)8 × 4 (D)8 × 8
rsiddana asked in Digital Logic Aug 12
by rsiddana
5 points
23 views
0 votes
0 answers 21 views
Morris Mano, Binary System, Question 1.14
For the weighted codes (a) 3, 3, 2, 1 and (b) 4, 4, 3, - 2 for the decimal digits, determine all possible tables so that the 9’s complement of each decimal digit is obtained by changing l’s to 0’s and 0’s to l’s
Sheldon asked in Digital Logic Aug 12
by Sheldon
5 points
21 views
0 votes
0 answers 21 views
Digital logic and Computer design by morris mano, Digital design by morris mano and michael d cilleti
ykrishnay asked in Digital Logic Aug 6
by ykrishnay
103 points
21 views
0 votes
0 answers 26 views
Digital Logic and Computer Design - Combinational Circuits
This_is_Nimishka asked in Digital Logic Jul 10
by This_is_Nimishka
5 points
26 views
0 votes
0 answers 23 views
#digital-logic
Suppose we are using 4-bit carry lookahead adder modules to built a 64-bit adder with a 2- level carry lookahead with ripple carry between the modules. if the delay of base gate(AND OR NOT) is 2 ns , then the worst case delay of 64 bit adder will be _______ ns?
Abhishek tarpara asked in Digital Logic Jul 5
by Abhishek tarpara
13 points
23 views
0 votes
0 answers 36 views
#testseries #digitallogic #kmap
Which of the following statements are correct? All prime implicants are minterms but all minterms are not prime implicants(PI). If a literal is deleted from a PI then it is no longer remains an implicant. in the k-map, cube corresponding to a prime implicant may be covered by larger cube. Essential prime implicant are those which are appear in final answer.
Abhishek tarpara asked in Digital Logic Jul 5
by Abhishek tarpara
13 points
36 views
0 votes
0 answers 28 views
Made Easy Postal course 2018 Number System
Result of subtraction while the following unsigned decimal number by taking the 10's complement of the subtrahend 1753-8640
Ananya Raj asked in Digital Logic Jun 26
by Ananya Raj
5 points
28 views
0 votes
0 answers 71 views
Applied Gate Practice Test
Consider the following counter. If the initial states of Q0(MSB) and Q1(LSB) are 0. What is the sequence Q0 Q1 given by the following diagram?
ketandalvi asked in Digital Logic Jun 13
by ketandalvi
5 points
71 views
0 votes
0 answers 36 views
Self Doubt(Digital Logic)
Maximum how many number of functions are possible so that F(x,y,z) = F(x,y’,z) ?
Kartik Goyal asked in Digital Logic Jun 5
by Kartik Goyal
5 points
36 views
0 votes
0 answers 27 views
Testbook Testseries
For implementing Boolean function F (A, B, C, D) = Σm (0, 1, 2, 4, 6, 9, 12, 14) using 8:1 multiplexer with select lines as B, C and D. Which of the following is correct? I0 and I2 are A̅ I0 and I2 are A I1, I3, and I4 are connected to A̅ I5, I6, and I7 are connected to 0
akabravo97 asked in Digital Logic May 20
by akabravo97
5 points
27 views
0 votes
0 answers 10 views
how to find the number of d flipflops required for implementing mod -k counter?
ramcharandevathi asked in Digital Logic May 6
by ramcharandevathi
5 points
10 views
0 votes
0 answers 24 views
GATE ECE PREVIOUS YEAR QUESTIONS BOOK
Atulvstar asked in Digital Logic Mar 6
by Atulvstar
5 points
24 views
1 vote
0 answers 47 views
TIFR 2020 Question 1 Computer Science section
Consider the following Boolean valued function on n Boolean variables: f(x1, ,xn)=x1+⋯+xn(mod 2), where addition is over integers, mapping FALSE' to 0 and TRUE' to 1. Consider Boolean circuits (with no feedback) that use only logical AND and OR gates, and ... 2^o(logn) n^c, for some fixed constant c n^ω(1), but n^O(logn) 2^Θ(n) None of the others
harleenkaur asked in Digital Logic Feb 28
by harleenkaur
9 points
47 views
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