Recent questions and answers in Digital Logic

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Final exam 2020-2021
If some T FFs are connected in series. The 1st FF is supplied by a clock with frequency 1 MHz and the last FF signal out is 31.25 KHz. Find the number of the Flip Flops are used in the circuit.

If some T FFs are connected in series. The 1st FF is supplied by a clock with frequency 1 MHz and the last FF signal out is 31.25 KHz. Find the number of the Flip Flops are used in the circuit.

asked 4 days ago in Digital Logic Emanjse 5 points 3 views

0 votes

0 answers 7 views

Applied Gate Practice Test
Consider the following counter. If the initial states of Q0(MSB) and Q1(LSB) are 0. What is the sequence Q0 Q1 given by the following diagram?

Consider the following counter. If the initial states of Q0(MSB) and Q1(LSB) are 0. What is the sequence Q0 Q1 given by the following diagram?

asked 6 days ago in Digital Logic ketandalvi 5 points 7 views

0 votes

1 answer 16 views

Self Doubt (Digital Logic Design)
A ⊕ B can be represented using 4 NAND gates as well as 5 NAND gates. Is there any predefined procedure to find the minimum number of NAND gate required by an expression?

A ⊕ B can be represented using 4 NAND gates as well as 5 NAND gates. Is there any predefined procedure to find the minimum number of NAND gate required by an expression?

answered Jun 8 in Digital Logic raun220 23 points 16 views

0 votes

1 answer 17 views

GeeksforGeeks
F(A,B,C)= A’+BC’ is functionally complete but how to derive AND(.) without using 1 or 0.

F(A,B,C)= A’+BC’ is functionally complete but how to derive AND(.) without using 1 or 0.

answered Jun 8 in Digital Logic raun220 23 points 17 views

0 votes

0 answers 9 views

Self Doubt(Digital Logic)
Maximum how many number of functions are possible so that F(x,y,z) = F(x,y’,z) ?

Maximum how many number of functions are possible so that F(x,y,z) = F(x,y’,z) ?

asked Jun 5 in Digital Logic Kartik Goyal 5 points 9 views

1 vote

1 answer 98 views

Self dout (Digital Logic Design)
Is the number of min terms always equal to the number of max terms , for a boolean function? Can we say that for a boolean function to be self dual, should satisfy the above condition as well as no mutual exclusive terms should be present?

Is the number of min terms always equal to the number of max terms , for a boolean function? Can we say that for a boolean function to be self dual, should satisfy the above condition as well as no mutual exclusive terms should be present?

answered May 24 in Digital Logic Deepakk Poonia (Dee) 1.7k points 98 views

0 votes

0 answers 14 views

Testbook Testseries
For implementing Boolean function F (A, B, C, D) = Σm (0, 1, 2, 4, 6, 9, 12, 14) using 8:1 multiplexer with select lines as B, C and D. Which of the following is correct? I0 and I2 are A̅ I0 and I2 are A I1, I3, and I4 are connected to A̅ I5, I6, and I7 are connected to 0

For implementing Boolean function F (A, B, C, D) = Σm (0, 1, 2, 4, 6, 9, 12, 14) using 8:1 multiplexer with select lines as B, C and D. Which of the following is correct? I0 and I2 are A̅ I0 and I2 are A I1, I3, and I4 are connected to A̅ I5, I6, and I7 are connected to 0

asked May 20 in Digital Logic akabravo97 5 points 14 views

0 votes

1 answer 18 views

2's complement
how did the range of 2’s complement is -2^(n-1) to (2^(n-1) -1)? particularly for the lower limit?

how did the range of 2’s complement is -2^(n-1) to (2^(n-1) -1)? particularly for the lower limit?

answered May 19 in Digital Logic Kanwae Kan 5 points 18 views

0 votes

1 answer 19 views

My college homework
Design a synchronous binary counter having the repeated binary sequence 0,2,4,6, 8, 10, 12, 14 using D flip-flops.

Design a synchronous binary counter having the repeated binary sequence 0,2,4,6, 8, 10, 12, 14 using D flip-flops.

answered May 19 in Digital Logic Kanwae Kan 5 points 19 views

0 votes

0 answers 11 views

Madeeasypostal ACE
"GATE CSE 2000 | Question: 1.6 - GATE Overflow" https://gateoverflow.in/629/gate-cse-2000-question-1-6 In question above we understood that positive number and unsigned is represented same as in 2's complement. here in question below the hex number is ... be same as number given is positive(bcoz msb is not 7). Determine 8's compliment of an octal number 2670? Right??

"GATE CSE 2000 | Question: 1.6 - GATE Overflow" https://gateoverflow.in/629/gate-cse-2000-question-1-6 In question above we understood that positive number and unsigned is represented same as in 2's complement. here in question below the hex number is unsigned because sign ... will be same as number given is positive(bcoz msb is not 7). Determine 8's compliment of an octal number 2670? Right??

asked May 11 in Digital Logic BhaktiDhorajiya 5 points 11 views

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1 answer 45 views

while solving a flip flop question i came around this situation.

is mod 1 counter possible?

answered May 6 in Digital Logic chris gyle 5 points 45 views

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2 answers 25 views

Principle of Duality (Digital Logic)
What will be the dual of the following expression? A + B’.[C’+D(E+F’)]

What will be the dual of the following expression? A + B’.[C’+D(E+F’)]

answered May 6 in Digital Logic chris gyle 5 points 25 views

0 votes

0 answers 8 views

how to find the number of d flipflops required for implementing mod -k counter?

asked May 6 in Digital Logic ramcharandevathi 5 points 8 views

0 votes

0 answers 11 views

ACE TEST SERIES
WHICH OF THE FOLLOWING INDICATES 8`s COMPLEMENT OF $[70700]_8$ IN SIX DIGIT? $[707100]_8$ $[007100]_8$ $[707078]_8$ $[007078]_8$

WHICH OF THE FOLLOWING INDICATES 8`s COMPLEMENT OF $[70700]_8$ IN SIX DIGIT? $[707100]_8$ $[007100]_8$ $[707078]_8$ $[007078]_8$

asked May 3 in Digital Logic abhishek.maurya 5 points 11 views

0 votes

0 answers 21 views

GATE ECE PREVIOUS YEAR QUESTIONS BOOK

asked Mar 6 in Digital Logic Atulvstar 5 points 21 views

1 vote

0 answers 30 views

TIFR 2020 Question 1 Computer Science section
Consider the following Boolean valued function on n Boolean variables: f(x1, ,xn)=x1+⋯+xn(mod 2), where addition is over integers, mapping FALSE' to 0 and TRUE' to 1. Consider Boolean circuits (with no feedback) that use only logical AND and OR gates, and ... 2^o(logn) n^c, for some fixed constant c n^ω(1), but n^O(logn) 2^Θ(n) None of the others

Consider the following Boolean valued function on n Boolean variables: f(x1, ,xn)=x1+⋯+xn(mod 2), where addition is over integers, mapping FALSE' to 0 and TRUE' to 1. Consider Boolean circuits (with no feedback) that use only logical AND and OR gates, and where each gate has two input bits, each ... n) is : 2^o(logn) n^c, for some fixed constant c n^ω(1), but n^O(logn) 2^Θ(n) None of the others

asked Feb 28 in Digital Logic harleenkaur 9 points 30 views

2 votes

3 answers 948 views

GATE CSE 2021 Set 2 | Question: 4 | Video Solution

The format of the single-precision floating point representation of a real number as per the $\text{IEEE 754}$ ... $=00000000$ and mantissa $=0000000000000000000000001$ exponent $=00000001$ and mantissa $=0000000000000000000000000$ exponent $=00000001$ and mantissa $=0000000000000000000000001$

asked Feb 18 in Digital Logic Arjun 257 points 948 views

3 votes

4 answers 835 views

GATE CSE 2021 Set 2 | Question: 5 | Video Solution

Which one of the following circuits implements the Boolean function given below? $f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6$, where $m_i$ is the $i^{\text{th}}$ minterm.

asked Feb 18 in Digital Logic Arjun 257 points 835 views

3 votes

2 answers 659 views

GATE CSE 2021 Set 2 | Question: 18 | Video Solution

If $x$ and $y$ are two decimal digits and $(0.1101)_2 = (0.8xy5)_{10}$, the decimal value of $x+y$ is ___________

asked Feb 18 in Digital Logic Arjun 257 points 659 views

4 votes

4 answers 2.5K views

GATE CSE 2021 Set 2 | Question: 44 | Video Solution

If the numerical value of a $2$-byte unsigned integer on a little endian computer is $255$ more than that on a big endian computer, which of the following choices represent(s) the unsigned integer on a little endian computer? $0\text{x}6665$ $0\text{x} 0001$ $0\text{x} 4243$ $0\text{x} 0100$

asked Feb 18 in Digital Logic Arjun 257 points 2.5K views

3 votes

2 answers 1.1K views

GATE CSE 2021 Set 2 | Question: 52 | Video Solution

Consider a Boolean function $f(w,x,y,z)$ such that $\begin{array}{lll} f(w,0,0,z) & = & 1 \\ f(1,x,1,z) & =& x+z \\ f(w,1,y,z) & = & wz +y \end{array}$The number of literals in the minimal sum-of-products expression of $f$ is _________

asked Feb 18 in Digital Logic Arjun 257 points 1.1K views

1 vote

4 answers 592 views

GATE CSE 2021 Set 1 | Question: 6 | Video Solution

Let the representation of a number in base $3$ be $210$. What is the hexadecimal representation of the number? $15$ $21$ $\text{D}2$ $528$

asked Feb 18 in Digital Logic Arjun 257 points 592 views

0 votes

4 answers 720 views

GATE CSE 2021 Set 1 | Question: 24 | Video Solution

Consider the following representation of a number in $\text{IEEE 754}$ single-precision floating point format with a bias of $127$.$S: 1\quad\quad E:\; 10000001\quad\quad F:\;11110000000000000000000$ Here $S, \;E$ and $F$ denote the ... components of the floating point representation. The decimal value corresponding to the above representation (rounded to $2$ decimal places) is ____________.

asked Feb 18 in Digital Logic Arjun 257 points 720 views

1 vote

3 answers 596 views

GATE CSE 2021 Set 1 | Question: 28 | Video Solution

Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states? $011,101,000$ $001,010,111$ $011,101,111$ $001,010,000$

asked Feb 18 in Digital Logic Arjun 257 points 596 views

2 votes

2 answers 636 views

GATE CSE 2021 Set 1 | Question: 42 | Video Solution

Consider the following Boolean expression. $F=(X+Y+Z)(\overline X +Y)(\overline Y +Z)$ Which of the following Boolean expressions is/are equivalent to $\overline F$ (complement of $F$)? $(\overline X +\overline Y +\overline Z)(X+\overline Y)(Y+\overline Z)$ $X\overline Y + \overline Z$ $(X+\overline Z)(\overline Y +\overline Z)$ $X\overline Y +Y\overline Z + \overline X \overline Y \overline Z$

asked Feb 18 in Digital Logic Arjun 257 points 636 views

0 votes

1 answer 44 views

Made easy test
Explain me this question with boolean function form.(not k map)

Explain me this question with boolean function form.(not k map)

answered Feb 5 in Digital Logic shantanu4raje 25 points 44 views

0 votes

0 answers 21 views

Made easy test
Explain me this question.

Explain me this question.

asked Feb 5 in Digital Logic Enolx.21 53 points 21 views

0 votes

1 answer 41 views

Made Easy Workbook
How can we minimize this function? Ans(d)

How can we minimize this function? Ans(d)

answered Feb 2 in Digital Logic zxy123 3.6k points 41 views

1 vote

0 answers 50 views

Self Doubt: Digital logic design
This question is from GATE 2019- Instrumentation branch (Digital logic) Can anyone solve this and can explain what is meant by steady state? Ans: 4

This question is from GATE 2019- Instrumentation branch (Digital logic) Can anyone solve this and can explain what is meant by steady state? Ans: 4

asked Jan 23 in Digital Logic phaneendrababu 11 points 50 views

1 vote

1 answer 36 views

GATE CSE 2004
Let A=1111 10101010 and B=0000 10101010 be two 8-bit 2′s complement numbers. Their product in 2′s complement is

Let A=1111 10101010 and B=0000 10101010 be two 8-bit 2′s complement numbers. Their product in 2′s complement is

answered Jan 23 in Digital Logic SarathBaswa 849 points 36 views

0 votes

1 answer 15 views

GATE CSE 2018
Consider the unsigned 8-bit fixed point binary number representation below b7 b6 b5 b4 b3 . b2 b1 b0 where the position of the binary point is between b3 and b2. Assume b7 is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation: (i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001

Consider the unsigned 8-bit fixed point binary number representation below b7 b6 b5 b4 b3 . b2 b1 b0 where the position of the binary point is between b3 and b2. Assume b7 is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation: (i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001

answered Jan 22 in Digital Logic Abhisheksmile94 347 points 15 views

1 vote

1 answer 19 views

Tga test series

answered Jan 12 in Digital Logic zxy123 3.6k points 19 views

0 votes

0 answers 22 views

Tga mock test
MSQ Type question.

MSQ Type question.

asked Jan 11 in Digital Logic Enolx.21 53 points 22 views

0 votes

0 answers 50 views

Made Easy Testseries Digital Q4
A flipflop has 3 ns delay from the time the clock edge occurs to the time the output is complemented. What is the maximum frequency at which mod-1024 counter can operate reliably? 33 MHz 40 MHz 33.3 MHz 10 MHz

A flipflop has 3 ns delay from the time the clock edge occurs to the time the output is complemented. What is the maximum frequency at which mod-1024 counter can operate reliably? 33 MHz 40 MHz 33.3 MHz 10 MHz

asked Jan 5 in Digital Logic Shivateja MST 45 points 50 views

0 votes

0 answers 79 views

#testquestion
#digital ckts number system GRE QUESTION Given ans is D... Post the detailed solution

#digital ckts number system GRE QUESTION Given ans is D... Post the detailed solution

asked Dec 29, 2020 in Digital Logic Amit puri 5 points 79 views

0 votes

1 answer 20 views

Applied Ai Test Series
2’s complement representation for (12121) base 3 ? 10010111 base 2 01011011 base 2 01011111 base 2 01011010 base 2

2’s complement representation for (12121) base 3 ? 10010111 base 2 01011011 base 2 01011111 base 2 01011010 base 2

answered Dec 22, 2020 in Digital Logic Deepakk Poonia (Dee) 1.7k points 20 views

0 votes

0 answers 19 views

Unacademy test series Digital Q2
Odd function B. Even Function C. Identity function D. Both B and C

Odd function B. Even Function C. Identity function D. Both B and C

asked Dec 19, 2020 in Digital Logic Shivateja MST 45 points 19 views

0 votes

1 answer 66 views

Unacademy Digital Quesn 1
A 1-bit full adder takes 20ns to generate a carryout bit and takes 40ns to generate a sum bit. The maximum rate of addition per second when four 1-bit full adder are cascaded is _______ x 10^7. Anyone please clarify.

A 1-bit full adder takes 20ns to generate a carryout bit and takes 40ns to generate a sum bit. The maximum rate of addition per second when four 1-bit full adder are cascaded is _______ x 10^7. Anyone please clarify.

answered Dec 18, 2020 in Digital Logic Sahil91 683 points 66 views

0 votes

1 answer 23 views

Self doubt - digital logic
K-map 0 1 0 0 0 1 X 0 0 X X 0 0 0 0 0 X= don’t care Derive the minimum Sum-of-Product form for this.

K-map 0 1 0 0 0 1 X 0 0 X X 0 0 0 0 0 X= don’t care Derive the minimum Sum-of-Product form for this.

answered Dec 17, 2020 in Digital Logic gajendercse 41 points 23 views

0 votes

0 answers 14 views

4-bit synchronous up-down counter designed using a T-flip flow.

Help me

asked Dec 16, 2020 in Digital Logic junpyo 5 points 14 views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

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