Recent questions and answers in Digital Logic - GATE CSE Doubts

+1 vote

1 answer

Tga test series

answered 4 days ago in Digital Logic by zxy123 (2.9k points) | 12 views

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Tga mock test
MSQ Type question.

asked 5 days ago in Digital Logic by Enolx.21 (25 points) | 16 views

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Made Easy Testseries Digital Q4
A flipflop has 3 ns delay from the time the clock edge occurs to the time the output is complemented. What is the maximum frequency at which mod-1024 counter can operate reliably? 33 MHz 40 MHz 33.3 MHz 10 MHz

asked Jan 5 in Digital Logic by Shivateja MST (45 points) | 22 views

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#testquestion
#digital ckts number system GRE QUESTION Given ans is D... Post the detailed solution

asked Dec 29, 2020 in Digital Logic by Amit puri (5 points) | 73 views

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1 answer

Applied Ai Test Series
2’s complement representation for (12121) base 3 ? 10010111 base 2 01011011 base 2 01011111 base 2 01011010 base 2

answered Dec 22, 2020 in Digital Logic by Deepakk Poonia (Dee) (1.5k points) | 15 views

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Unacademy test series Digital Q2
Odd function B. Even Function C. Identity function D. Both B and C

asked Dec 19, 2020 in Digital Logic by Shivateja MST (45 points) | 16 views

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1 answer

Unacademy Digital Quesn 1
A 1-bit full adder takes 20ns to generate a carryout bit and takes 40ns to generate a sum bit. The maximum rate of addition per second when four 1-bit full adder are cascaded is _______ x 10^7. Anyone please clarify.

answered Dec 18, 2020 in Digital Logic by Sahil91 (645 points) | 30 views

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1 answer

Self doubt - digital logic
K-map 0 1 0 0 0 1 X 0 0 X X 0 0 0 0 0 X= don’t care Derive the minimum Sum-of-Product form for this.

answered Dec 17, 2020 in Digital Logic by gajendercse (41 points) | 19 views

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4-bit synchronous up-down counter designed using a T-flip flow.

asked Dec 16, 2020 in Digital Logic by junpyo (5 points) | 9 views

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Made easy Digital Logic Q1
Anyone please clarify. I feel answer to be 16 ms.

asked Dec 15, 2020 in Digital Logic by Shivateja MST (45 points) | 32 views

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Question taken from book morris mano 3rd edition chapter 3 question number 26

asked Dec 14, 2020 in Digital Logic by fahad137 (5 points) | 11 views

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1 answer

#self-doubt #logic-design
IN excess 3 code -The binary sum of a code and its 9′s complement is equal to 9. can someone explains meaning of this statement with example.

answered Dec 7, 2020 in Digital Logic by Sahil91 (645 points) | 17 views

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Made Easy test series
How to know through representation which one is LSB and which one is MSB

asked Dec 3, 2020 in Digital Logic by vimal12 (5 points) | 16 views

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1 answer

Made Easy TextBook Assignments Counters #self doubt

answered Dec 2, 2020 in Digital Logic by zxy123 (2.9k points) | 20 views

+2 votes

1 answer

NLCIL2020(PSU)
Q.1) what is minimum number of NAND gate require to implement the function$A^{'}C^{'}+B^{'}C^{'}+CD$.there is only 2-input NAND gate available.

answered Nov 30, 2020 in Digital Logic by _sajalrai_ (563 points) | 39 views

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Made Easy Text Book Counters 2018 Delay of ripple counter and synchronous counter

asked Nov 30, 2020 in Digital Logic by ayusha5312 (21 points) | 11 views

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Made Easy Text Book Counters 2018 Delay of ripple counter and synchronous counter

asked Nov 30, 2020 in Digital Logic by ayusha5312 (21 points) | 14 views

+3 votes

1 answer

Gateoverflow test series question.
Assume that the propagation delay in each gate in a 16-bit ripple carry adder (made of AND, OR, and NOT gates only with up to 3 inputs) is 1 ns. Time taken in nanoseconds to perform a 16-bit addition is _______. Given answer is 33 nanoseconds. How to solve this question?

answered Nov 29, 2020 in Digital Logic by _sajalrai_ (563 points) | 78 views

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Made Easy TextBook Counters Gate CS .#Self Doubt
Please provide detailed solution.

asked Nov 29, 2020 in Digital Logic by ayusha5312 (21 points) | 27 views

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NIC STA 2020 SET A 54
Q. How many AND, OR and XOR gate are required for implementation of full adder? A) 1,2,2 B) 2,2,1 C) 3,2,2 D) 3,0,1 I think none of the option match Plz check

asked Nov 27, 2020 in Digital Logic by Hradesh patel (5 points) | 11 views

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NiC STA 2020 set A 111
Q. Encoder are made by three.......gates. A) AND B) OR C) NAND D) XOR I think question framing wrong Plz check

asked Nov 27, 2020 in Digital Logic by Hradesh patel (5 points) | 17 views

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1 answer

Made Easy Sequential Circuits 2018 #self doubt
Please provide the detailed solution!

answered Nov 26, 2020 in Digital Logic by zxy123 (2.9k points) | 15 views

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NIELIT NIC STA 2020 set-C ques 100
Which flip flop is used to make all type of shift registers? JK flipflop D flipflop T flipflop all options using D we can obviously make all shift registers but cant we use JK or any other flip flop to do so?

asked Nov 26, 2020 in Digital Logic by ayush.5 (99 points) | 15 views

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1 answer

NIELIT NIC scientist-B 2020 set-C ques 51
X Y X$Y 1 0 1 1 1 1 0 1 0 0 0 1 Identify the matching boolean expression. X$~Y ~X$Y ~X$~Y none of the options

answered Nov 26, 2020 in Digital Logic by zxy123 (2.9k points) | 13 views

+1 vote

1 answer

Made Easy Text Book Sequential Circuit #2018 #JK Flip Flops

answered Nov 25, 2020 in Digital Logic by zxy123 (2.9k points) | 13 views

0 votes

1 answer

Made Easy Test Series, Digital Logic , Combinational Circuits

answered Nov 24, 2020 in Digital Logic by ayusha5312 (21 points) | 50 views

+1 vote

1 answer

MadeEasy textbook Digital logic combinational circuits

answered Nov 23, 2020 in Digital Logic by zxy123 (2.9k points) | 21 views

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1 answer

MadeEasy text book Digital logic Combinational circuits 2018

answered Nov 23, 2020 in Digital Logic by zxy123 (2.9k points) | 18 views

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Made Easy test Series
F is a boolean function in 4 boolean variables x,y,z, and w. $F(x,y,z,w) = \sum \left ( 0,1,4,11,12,13,15 \right )$ Then the expression for the dual of F is: Solution: I could not understand the 2nd line, If $F$ is $0$ for term $x$ ... I could not understand, why would $(2^4 -1- x)$ be a minterm of $F^d$. Please if someone could explain would be of great help. Thanks!

asked Nov 22, 2020 in Digital Logic by Sarrthak (5 points) | 22 views

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Sequential Circuit
Draw the sequential circuit for serial adder using shift registers, full adder and D-FF. Explain its operation with state equations and state table .

asked Nov 19, 2020 in Digital Logic by Asad5059 (5 points) | 14 views

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Will Download B.S. Grewals in Higher Mathematics bring antivirus？

asked Nov 18, 2020 in Digital Logic by Ellalucky (5 points) | 14 views

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1 answer

#made-easy-test-series
Number of literals present in the boolean expression given below: cd+b(comp.)d(comp.)+ac+a(comp)bd ans in solution is 9 did we have to count literal in each and every term uniquely or we have to count only unique literals (then ans will be 4).

answered Nov 16, 2020 in Digital Logic by zxy123 (2.9k points) | 14 views

+1 vote

1 answer

made easy grand test question

answered Nov 15, 2020 in Digital Logic by zxy123 (2.9k points) | 52 views

+1 vote

1 answer

Self Doubt:Digital
How many PI's are there in below K-map? X 1 1 0 0 X 0 1 X X X 1 0 0 X 1 I hope there will be 6 PI's. But if the highlighted pair of only don't care is considered as PI's, then pair will be 7. I hope only donot care ... ) on a Karnaugh map which is not subsumed by any other implicant in the same map. link:https://en.wiktionary.org/wiki/prime_implicant Someone confirm the final ans

answered Nov 14, 2020 in Digital Logic by zxy123 (2.9k points) | 28 views

+1 vote

1 answer

made easy test series
Consider the Johnson counter shown in the figure below. The clock applied to the counter is also shown: Let the initial state of Johnson counter be 0000. Consider the delay from input to output of each flip-flop is 0.1 ms. After how much time (in ms) the output of the counter will be all zero again?

answered Nov 8, 2020 in Digital Logic by zxy123 (2.9k points) | 40 views

+1 vote

1 answer

made east test series
The clock frequency of 12 MHz is applied to a cascaded counter of modulus-3 counter, modulus-4 counters and modulus-5 counters. The lowest output frequency will be ________ (in KHz). The solution is given as =12/(3*4*5).I didnt understand why they divided?

answered Nov 7, 2020 in Digital Logic by zxy123 (2.9k points) | 33 views

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1 answer

applied gate test series : finding number of prime implicants in presence of don't cares

answered Oct 29, 2020 in Digital Logic by SarathBaswa (633 points) | 40 views

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2 answers

Madeeasy Testseries question
III only IV only I, II, III only I, II, IV only Clearly IV is wrong and III is right. I feel I and II need not be true. Anyone please clarify.

answered Oct 28, 2020 in Digital Logic by ayush.5 (99 points) | 60 views

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1 answer

Applied Gate test Series - Digital Logic - JK Flip Flop

answered Oct 26, 2020 in Digital Logic by deCiFer598 (5 points) | 26 views

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1 answer

Made Easy Test Series
Please help me! BCD number here given are positive(0 -9) and we know that the 9’s complement of a positive number is that number itself. Then why they have subtracted each BCD number from 9? And suppose if I take the 9’s complement of a number for instance “7” that would be 2. Doesn't it means that 2 represent a negative number that is -7?

answered Oct 22, 2020 in Digital Logic by kalin (153 points) | 40 views

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