Recent questions and answers in Digital Logic - GATE CSE Doubts

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GATEBOOK MOCK TEST 1 Q49
A sequence detector has to be designed to detect a sequence with at most 3 runs of consecutive zeros of length 3. 001000010001000 This sequence has exactly 2 such runs If we implement a sequential circuit with J-K flip flops then minimum number of flip flops required is ----?

asked 3 days ago in Digital Logic by Rajat Maheshwari (10 points) | 4 views

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ravinder ravula
How to find the characteristic equation of this? [closed]

asked 4 days ago in Digital Logic by meivinay (7 points) | 10 views

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gatebook test sereis: Digital logic
A sequence detector has to be designed to detect a sequence with at most 3 runs of consecutive zeros of length 3. 001000010001000 This sequence has exactly 2 such runs If we implement a sequential circuit with J-K flip flops then minimum number of flip flops required is ----?

asked 4 days ago in Digital Logic by vikas999 (55 points) | 10 views

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fliflops and counters basic doubt
can jhonson counters be implemented using JK flipflop?

asked 4 days ago in Digital Logic by Divyaok (20 points) | 6 views

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ME Test Propagation Delay

asked 5 days ago in Digital Logic by kashyap02 (11 points) | 9 views

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MADE EASY MULTI SUBJECT DIGITAL DOUBT
ANSWER GIVEN IS 6. BUT I AM GETTING ANSWER AS 4. PLEASE CHECK AND CONFIRM.

asked 5 days ago in Digital Logic by SuvasishDutta (163 points) | 20 views

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GATE GURU: WORK BOOK
Binary to Gray Binary to excess 3 Gray to Binary BCD to binary

asked 5 days ago in Digital Logic by Debapaul (619 points) | 16 views

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MADE EASY ADVANCE LEVEL DIGITAL
$\sum m(2,3,6,7)$ $\sum m(0,1,2,3)$ $\sum m(0,1,4,5)$ $\sum m(4,5,6,7)$

answered 6 days ago in Digital Logic by shashin (1.2k points) | 17 views

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MADE EASY FLT: ADVANCE DIGITAL LOGIC
A boolean function $f(A,B,C)=AB’C$ is being implemented using minimum number of $2$ $input$ $NOR$ gates.Each gate is having a propagation delay of $2ns$.What is the overall delay of the circuit? I face a lot of difficulty in solving these types of problems. How to be certain that the circuit u designed contains minimum number of gate?

asked 6 days ago in Digital Logic by Debapaul (619 points) | 31 views

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Self Doubt: Counters
Suppose there is a MOD 6 synchronous counter with 1 AND gate as clearing circuit. If I want to make it MOD 7(ie. count 7 states instead on 6), would I have to introduce a 1 clock delay, or 2 clock delay in the AND gate? Ref: https://gateoverflow.in/151216/digital-electronics-ece-set-3-gate-2016

asked Jan 9 in Digital Logic by Sambhrant Maurya (336 points) | 10 views

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Made Easy Full Length Test 1

answered Jan 9 in Digital Logic by shashin (1.2k points) | 53 views

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Made Easy test series multiple subject digital adder

asked Jan 8 in Digital Logic by Ram Swaroop (155 points) | 11 views

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Self-doubt XOR
How in XOR no of minterms are equal to no of maxterms?

answered Jan 7 in Digital Logic by shashin (1.2k points) | 21 views

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Made easy test series : Number system
Consider a modified 8-bit floating point representation in which 1-bit for sign, 3-bit for exponent and 4-bit for significant. What will be representation for decimal value –12? What is the bias value we have to take for above question?

answered Jan 7 in Digital Logic by yadavg123 (17 points) | 21 views

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TestSeries Doubt
Options are A).1.7 B).2.4 C).3.5 D).3.3 Please provide the solution also :)

asked Jan 5 in Digital Logic by pass_i0n (14 points) | 11 views

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MadeEasyFULL SYLLABUS TEST-5 (ADVANCE LEVEL) GATE 2020 Q47

asked Jan 5 in Digital Logic by DukeThunders (408 points) | 16 views

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Made Easy : Self Doubt
Is MUX functionally complete? and with a $8:1$ $MUX$ can we obtain all function of 3 variables?

asked Jan 4 in Digital Logic by Debapaul (619 points) | 7 views

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Self Doubt: Digital
$Proof$ $y+\overline{x}$ $\overline{y}= y+ \overline{x}$ Don’t proof it using table method, I want to know how u solved the $LHS$ to get the $RHS?$

answered Jan 2 in Digital Logic by Pratyush Priyam Kuan (740 points) | 25 views

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Geeks_MockGate2020
We have a 8-bit ripple carry adder which is implemented by Cascading Full adders. Full adders are also made by the combination of OR, AND and XOR gate. Assume that Sum has 8 ns delay and Carry has 6 ns delay. Find the time taken to find the sum in the worst case.

answered Jan 1 in Digital Logic by STUDYGATE2019 (39 points) | 43 views

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MOCK EXAM ACE
Consider the following statements regarding counters: S1 : The Hamming distance of an Overbeck counter is 1 and the Hamming distance of a Johnson counter is 2. S2 : Only output sequence 0, 8, 12, 14, 15, 7, 3, 1, 0, ... is possible in Overbeck counter but not output sequence 2, ... S2, S3 are false and S1 is true (C) Only S1, S3 are false and S2 is true (D) All S1, S2, and S3 are true

answered Dec 31, 2019 in Digital Logic by poonamc (9 points) | 36 views

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madeeasy FULL SYLLABUS TEST-6 (ADVANCE LEVEL) GATE 2018 Q41

asked Dec 30, 2019 in Digital Logic by DukeThunders (408 points) | 19 views

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MOCK DEMO madeeasy Q18
Both f and g are functionally complete. only f is functionally complete. only g is functionally complete neither f nor g is functionally complete. please describe the procedure

answered Dec 30, 2019 in Digital Logic by Pratyush Priyam Kuan (740 points) | 40 views

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Self Doubt: Floating point representation
What is the smallest number representable in IEEE single precision floating point representation? $Sign$ $Exponent$ $Mantissa$ $0$ $00000001$ $00000000000000000000000$ So the smallest number is $1 * 2^-$^1$^2$^6$ Is this correct?

asked Dec 30, 2019 in Digital Logic by Debapaul (619 points) | 17 views

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MadeEasy FULL SYLLABUS TEST-3 (BASIC LEVEL) GATE 2020 - Q18 Gray code

asked Dec 30, 2019 in Digital Logic by DukeThunders (408 points) | 20 views

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Combinational Circuits
What is the minimum size of the ROM required to implement the following set of Boolean equations? F1(w,x,y,z) = $\sum$ m(0, 1, 2, 5, 7, 12, 13, 15) F2(w,x,y,z) = $\sum$ m(0, 5, 6, 9, 13, 15) F3(w,x,y,z) = $\sum$ m(6, 7, 9, 12, 14,15) (a) 16 $\times$ 4 (b) 16 $\times$ 3 (c)16 $\times$ 8 (d) 16 $\times$ 12

asked Dec 30, 2019 in Digital Logic by haralk10 (54 points) | 11 views

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'n' flip flops will divide the clock frequency by a factor of

asked Dec 30, 2019 in Digital Logic by manu.ratheesh (6 points) | 24 views

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Digital self doubt active high active low chip
How do I identify if a chip is active high or active low. Here they have taken it as active low. But there is no bar on Cr. Is the bubble input enough to identify it as an active low chip. Sometimes I have seen both bubble input and bar on Cr where the chip was treated as active low. I’m confused. Kindly help me. Thanks.

asked Dec 29, 2019 in Digital Logic by DukeThunders (408 points) | 18 views

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Combinational circuit
A structure using which can provide half adder as well as half subtractor?

asked Dec 29, 2019 in Digital Logic by Shrenik97 (6 points) | 4 views

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GATE 2015 Modified Question
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is ... AHEAD adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.

asked Dec 27, 2019 in Digital Logic by Debapaul (619 points) | 40 views

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Gatebook Practice Question::Number System
Consider the 16-bit floating-point format which has 9 rightmost bits for the mantissa and 6 bits for the excess-31 exponent in the middle and most significant bit stands for sign of the float number. Which of the following represents the difference ... Answer given as: A Please someone explain where I am going wrong and if not, is my solution correct?

answered Dec 23, 2019 in Digital Logic by Satbir (4.1k points) | 35 views

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Geeks_for_Geeks
Consider the following minterm representation of the function F(x,y,z)=∑(1,2,3,4,5), how many two input NAND gates are required to implement this function, assume that all the inputs and their complements are available.

asked Dec 19, 2019 in Digital Logic by shubham02 (14 points) | 11 views

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Ravindrababu test series
a).11 b)10 c) 9 d)12 & Please Explain the method to solve also:) [closed]

asked Dec 19, 2019 in Digital Logic by pass_i0n (14 points) | 27 views

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Doubt in DELD
In this image is EPI-2 is really essential PI? as we can cover 1 (wxy’z’ ) also by PI of size 2(marked by blue line).

asked Dec 16, 2019 in Digital Logic by mehul vaidya (13 points) | 9 views

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Made Easy Digital Logic
The minimum no. of NAND gates needed to implement the function $Y=(B+C)(A'+D')$ is? Is there a general procedure for this? I get it wrong many times. I converted it to SOP to get Y = BA’ + BD’ + CA’ + CD’ which cannot be further minimized, giving 5 NAND gates. But the ans is 4 :(

asked Dec 15, 2019 in Digital Logic by Sambhrant Maurya (336 points) | 12 views

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dld number system
(516) base 7 =() base 2 MINIMUM NUMBER OF BITS REQUIRED TO REPRESENT IN BINARY???

answered Dec 13, 2019 in Digital Logic by amit166 (138 points) | 4 views

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GATE 2018 EE
The circuit below shows an up/down counter working with a decoder and a flipflop. Preset and Clear of the flip-flop are asynchronous active-low inputs. Assuming that the initial value of counter output (Q2Q1Q0) as zero, the counter output in decimal for 12 clock cycles are (A) 0, 1, 2, 3, 4, 4, 3, 2, 1, 1, 2, 3, ... 3, 4, 5, 5, 4, 3, 2, 1, 0, 1 (D) 0, 1, 2, 3, 4, 5, 4, 3, 2, 1, 0, 1, 2

asked Dec 13, 2019 in Digital Logic by Sambhrant Maurya (336 points) | 4 views

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GATE 2003 IN
The square wave $C_{1}$ shown in the figure is given to the clock input of a 4-bit binary up/down counter whose UP/ DN input is fed with the pulse train $P_{U}$. The counter is a negative edge triggered one. The counter starts with 0000 and will reach 0000 again at the (A) 15th clock pulse (B) 16th clock pulse (C) 44th clock pulse (D) 48th clock pulse

asked Dec 13, 2019 in Digital Logic by Sambhrant Maurya (336 points) | 3 views

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Self Doubt: K maps
$f_{1}(A,B,C,D) = \sum(0,1,8,9) + d(2,10,5)$ $f_{2}(A,B,C,D) = \sum(0,2,9,14) + d(1,8,15)$ Then what is f1 + f2 and f1 . f2 respectively? How to deal with the don’t cares? [closed]

asked Dec 12, 2019 in Digital Logic by Sambhrant Maurya (336 points) | 9 views

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1 answer

answered Dec 12, 2019 in Digital Logic by gull kaur (10 points) | 10 views

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Made Easy: Digital Logic
In the logic circuit above, input at line $I_{13}$ in 16 X 1 MUX corresponds to output at line $I'_{n}$ of 1 X 16 DeMUX. What is the value of n?

asked Dec 11, 2019 in Digital Logic by Sambhrant Maurya (336 points) | 17 views

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