Recent questions and answers in Digital Logic

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Decidability Problem (Rice University pdf)
For the following language, state whether language is (I) recursive, (II) recursively enumerable but not recursive, or (III) not recursively enumerable. Prove your answer. $L_{11} = \{<M_{1}, M_2> | \text{ M}_1 \text{and M}_2 \text{ are two TMs}, \text{and } \epsilon \in L(M_1) \backslash L(M_2) \}$

answered 11 hours ago in Digital Logic by Arjun (114 points) | 29 views

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Why T=2*t-pd In the answer and total no: of gate is not odd also!

asked 2 days ago in Digital Logic by kalra05 (112 points) | 11 views

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Should I cover HDL for gate exam?

asked 2 days ago in Digital Logic by Hyp209 (102 points) | 6 views

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How to solve such question.
The number of 1's in 8-bits representation of -127 in 2's complement form is m and that in 1's complement form is n. What is the value of m : n? Options are: 2:1 1:2 3:1 1:3

answered 3 days ago in Digital Logic by kalra05 (112 points) | 5 views

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Made easy Test series!!

asked 3 days ago in Digital Logic by kalra05 (112 points) | 6 views

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GATEBOOK Floating point 16 bit
Consider the 16 bit floating-point format which has 9 rightmost bits for the mantissa and 6 bits for the excess-31 exponent in the middle and most significant bit stands for sign of the float number. Which of the following represents the difference between the smallest and third ... positive float value in this system? $2^{-39}$ $2^{-40}$ $2^{-38}$ $2^{-37}$

answered 3 days ago in Digital Logic by kalra05 (112 points) | 19 views

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Describe the difference between following three 1st order logic formula

answered 4 days ago in Digital Logic by Satbir (1k points) | 6 views

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Digital Doubt regarding minimal and irredundant expression

answered 5 days ago in Digital Logic by `JEET (159 points) | 12 views

+1 vote

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Self doubt : $2's$ complement
Why $2’s$ complement operation generally used for subtraction?

answered 5 days ago in Digital Logic by `JEET (159 points) | 15 views

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Gatebook Floating Point
Consider the 16-bit floating-point format which has 9 rightmost bits for the mantissa and 6 bits for the excess-31 exponent in the middle and most significant bit stands for sign of the float number. Which of the following represents the difference between the largest and eighth largest normalized positive float value in this system? $2^{22}$ $2^{23}$ $2^{24}$ $2^{25}$

answered 5 days ago in Digital Logic by srestha (247 points) | 37 views

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GATEBOOK - IEEE754 Hexadecimal to Decimal
Which of the following real numbers represents IEEE-754 standard single precision floating point value $0x40200000$ to its correct decimal value: 2.5 3.5 4.125 5.125

answered 5 days ago in Digital Logic by srestha (247 points) | 8 views

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Vani Question Bank:Digital
A 4 bit parallel binary adder is built using four full adders. If each full adder takes 52ns to produce the sum bit and 20ns to produce carry bit, then the time required for addition of two 4-bit numbers is __________ns.

asked Aug 14 in Digital Logic by Hirak (1.3k points) | 8 views

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Self doubt: Digital logic 1
Is it a counter circuit?How to recognize ? If all flip-flop are reset state at first, what is it’s output at Y after $5$ th clock pulse?

answered Aug 11 in Digital Logic by user2525 (1.6k points) | 21 views

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Made Easy Test Series: Digital Logic-IEEE double precision

asked Aug 10 in Digital Logic by srestha (247 points) | 5 views

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number system
the value of X,Y,if$(X567)_{8}+(2YX5){_{8}}$ = $(71YX){8}$

answered Aug 10 in Digital Logic by Rudr Pawan (419 points) | 11 views

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Digital logic doubt
K-map can be used upto n variables. What is the value of n ? Is it 5 ?

asked Aug 7 in Digital Logic by user2525 (1.6k points) | 17 views

+3 votes

2 answers

Self doubt: implicants
How many implicant, prime implicant and essential prime implicants are present in the given k-map

answered Jul 29 in Digital Logic by Satbir (1k points) | 45 views

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Gradeup Quiz digital logic
A 1-input, 2-output synchronous sequential circuit behaves as follows: Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk+nk=k). The circuit outputs 00 until one of the following conditions holds. ... is 01. What is the minimum number of states required in the state transition graph of the above circuit? pls explain the question

asked Jul 26 in Digital Logic by aditi19 (134 points) | 8 views

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2 answers

Test serios questions 8

answered Jul 24 in Digital Logic by APOORV PANSE (190 points) | 20 views

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2 answers

Test serious question 23

answered Jul 24 in Digital Logic by APOORV PANSE (190 points) | 19 views

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1 answer

Made easy test series dld

answered Jul 24 in Digital Logic by APOORV PANSE (190 points) | 13 views

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Solve the question

asked Jul 24 in Digital Logic by Deepak Yadav (102 points) | 17 views

+1 vote

1 answer

Test series Made easy
Minimum no. of NOR gates required to implement ===> (A+B+C)’ ?

answered Jul 23 in Digital Logic by APOORV PANSE (190 points) | 6 views

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1 answer

Test book question 23

answered Jul 21 in Digital Logic by Debargha Bhattacharj (1.3k points) | 21 views

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Test book question 40 41 42
image widget

asked Jul 20 in Digital Logic by Deepalitrapti (138 points) | 6 views

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1 answer

Made easy digital electronics
Can A number in number system other then decimal be squared using same way as one does with decimal if not how come the first step of solution.

answered Jul 20 in Digital Logic by Debargha Bhattacharj (1.3k points) | 8 views

+1 vote

1 answer

Test book questions 41

answered Jul 20 in Digital Logic by Lakshman Patel RJIT (127 points) | 11 views

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Made Easy Workbook Sequential Circuit
In the below question no. 2 , the initial state is given as per solution is Q0 = 1 , Q1 = 0 , Q2 = 0 . Can anyone show the circuit table and what will be the final answer ?

asked Jul 18 in Digital Logic by user2525 (1.6k points) | 3 views

+1 vote

1 answer

Virtual Gate Test series

answered Jul 16 in Digital Logic by Hirak (1.3k points) | 28 views

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2 answers

Digital electronics worksheet from my coaching institution

answered Jul 15 in Digital Logic by Debargha Bhattacharj (1.3k points) | 15 views

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Virtual Gate
In the circuit shown in figure, value of input P goes from 0 to 1 and that of Q goes from 1 to 0. Which output forms shown in figure represents the output under a static hazard condition? [closed]

asked Jul 15 in Digital Logic by aditi19 (134 points) | 8 views

+1 vote

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if x and y are boolean variables which of the following is the equivalent of x xor y xor xy

asked Jul 15 in Digital Logic by shabanam (103 points) | 17 views

–1 vote

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Made easy test series digital logic

asked Jul 14 in Digital Logic by Shivani Santoshi (101 points) | 22 views

+1 vote

1 answer

Self Doubt Digital Logic
In a 4-bit carry look ahead adder, the propagation delay of EX-OR gate is 20 ns, AND and OR gates is 10 ns. The sum and carry output of full adder takes 20 ns and 10 ns respectively. The total propagation delay of the above adder in ns is ?

answered Jul 10 in Digital Logic by user2525 (1.6k points) | 28 views

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Self Doubt:Digital Logic
A number has 25 decimal digits. The minimum number of bits required for its representation in binary is?

answered Jul 10 in Digital Logic by Verma Ashish (305 points) | 11 views

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VirtualGate Test Series 2018
A microprocessor has an instruction XOR(r1, r2) which performs an Exclusive OR operation of registers r1, r2 and stores the result in r1. After the following instructions are executed XOR(r2, r1) XOR(r1, r2) XOR(r2, r1) Which one of the ... r2 is half sum of r1 and r2 Contents of registers r1 and r2 remain unaltered Contents of registers r1 and r2 are registered

asked Jul 9 in Digital Logic by Sambhrant Maurya (281 points) | 5 views

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VirtualGate test series 2019
In the circuit shown in figure, value of input P goes from 0 to 1 and that of Q goes from 1 to 0. Which output forms shown in figure represents the output under a static hazard condition?

asked Jul 9 in Digital Logic by Sambhrant Maurya (281 points) | 11 views

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Self doubt: Digital Logic
What are synchronous series carry and parallel carry counters?

asked Jul 9 in Digital Logic by Sambhrant Maurya (281 points) | 5 views

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1 answer

GateForum Test Series: Digital Logic
The number of BCD numbers that can be uniquely represented in 2-4-2-1 code is? _______

answered Jul 9 in Digital Logic by Debargha Bhattacharj (1.3k points) | 11 views

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GateBook Test series: Digital Logic
A sequence detector has to be designed to detect a sequence with at most 3 runs of consecutive zeros of length 3. 001000010001000 This sequence has exactly 2 such runs If we implement a sequential circuit with J-K flip flops then minimum number of flip flops required is ----?

asked Jul 7 in Digital Logic by Sambhrant Maurya (281 points) | 14 views