Recent questions and answers in Digital Logic - GATE CSE Doubts

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Testbook:Mock
The min-term representation of the function Y=A⊙B⊙C⊙D is

answered Mar 24 in Digital Logic by smsubham (64 points) | 14 views

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ISI 2020 -PCB- cs mtech
When we add a pair of two-bit binary numbers, say ab and cd, we get a number of at most three bits, say pqr. Using standard operators of Boolean algebra, namely AND (∧), OR (∨) and NOT (¬), derive the Boolean expressions of p, q and r in terms of a, b, c and d.

asked Mar 24 in Digital Logic by Dn0047 (10 points) | 8 views

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GATE2001-11-b
Please solve this. I didn’t understand the approach. https://gateoverflow.in/203826/gate2001-11-b

asked Mar 23 in Digital Logic by varunraj (6 points) | 14 views

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ISI SAMPLE PAPER (2020)
When we add two pairs of tow-bit binary numbers, say ab and cd, we get a number of at most three bits, say pqr. Using standard operators of Boolean algebra namely AND(^),OR(V),NOT, derive the Boolean expressions of p,q, and r in terms of a,b,c and d.

asked Mar 23 in Digital Logic by Dn0047 (10 points) | 3 views

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r's and (r-1)'s complement in Digital Logic
1. Should a positive number be represented using complement? 2. Can a positive number be represented using complement? 3. What is the purpose of complementing a number? 4. can we add two positive numbers using 1's complement or 2's complement form?

asked Mar 19 in Digital Logic by rajenderashwin (8 points) | 11 views

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Appsc polytechnic lecturer 2020
Can anyone explain the logic behind this.

asked Mar 19 in Digital Logic by Syedarshadali (6 points) | 13 views

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APPSC Polytechnic Lecturer
A 64-bit full adder is designed using half-adders, where each I-bit full adder module has the same structure. If each half adder is formed using 2-input NAND gates only, then estimate the total number of 2-input NAND gates required for such a 64-bit full adder.

asked Mar 16 in Digital Logic by Manohar Reddy (6 points) | 8 views

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Functionally Complete
Is a Demultiplexer functionally complete? Here two answers are giving contrasting answers. https://electronics.stackexchange.com/questions/104923/is-demultiplexer-universal-gate/104944

asked Mar 4 in Digital Logic by smsubham (64 points) | 5 views

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General Question about book to refer
Hello, the topic of NUMBER REPRESENTATION is not covered well in the Morris Mano textbook. does anyone know of any book that covers it sufficiently for GATE ?? thanks.

answered Mar 2 in Digital Logic by !KARAN (351 points) | 28 views

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Counter Design
Use the minimum number of D- Flip Flops and logic gates to design a counter that produces the following repeated sequence: 0,1,3,5,6,7,0….and gives an output of 1 when it reaches 7. How to produce output of 1 at state 7?

asked Feb 19 in Digital Logic by Abhipsa (17 points) | 14 views

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Overflow -ACE FLT
Why here XNOR is using instead of XOR?? I havenot got their explanation too.Plz someone elaborate

asked Feb 1 in Digital Logic by srestha (683 points) | 26 views

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MADE EASY TEST SERIES question on delay in flip flops

asked Feb 1 in Digital Logic by Ashutosh07091999 (7 points) | 14 views

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Self Evaluation: Ask me some question on minimum number of 2 input NOR and NAND required to realize a circuit

asked Jan 28 in Digital Logic by Debapaul (699 points) | 59 views

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made easy mock 1 dld

asked Jan 27 in Digital Logic by Vignaneswarkrishna (14 points) | 23 views

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Floating Point Arithmetic
What is the result of evaluating the following two expressions using three digit floating point arithmetic using three digit floating point arithmetic with rounding: B: 113. + (-111. + 7.51) The method I've learnt is that we first convert all the numbers into scientific notation. Then ... Is this the correct method of solving this?

asked Jan 25 in Digital Logic by goxul (377 points) | 34 views

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Self doubt:MADE EASY: COUNTERS
Is there any other states in the output other than $000$ and $111?$ All the flips flops are given only $toggle$ input right? So shouldnt it be $mod2$ counter?

asked Jan 24 in Digital Logic by Debapaul (699 points) | 16 views

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Need Explanation
Somebody explain this question.

answered Jan 24 in Digital Logic by shashin (1.9k points) | 27 views

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Made easy test series, DLD-Counters
How is it mod-5 counter?please explain

answered Jan 24 in Digital Logic by shashin (1.9k points) | 60 views

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floating point representation
How to represent 5.5 decimal no in the IEEE 754(single precision format) using normal bias and with and without using normalization.

answered Jan 24 in Digital Logic by namekrakhnu (14 points) | 24 views

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Self Doubt in MSB and LSB.
How to take MSB and LSB? I mean answer changes or the pattern changes when MSB and LSB is changed. Can you please tell the important points regardng this.

asked Jan 24 in Digital Logic by CSHuB (16 points) | 13 views

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testbook advance 3 counter
above circuit is: MOD 7 UP COUNTER MOD 13 UP COUNTER MOD 1 UP COUNTER MOD 1 DOWN COUNTER

asked Jan 23 in Digital Logic by abhinav649 (67 points) | 12 views

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Digital logic Ace test series

answered Jan 21 in Digital Logic by shashin (1.9k points) | 44 views

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ace test series mock test 7
8.

asked Jan 21 in Digital Logic by Rahul Burman (21 points) | 20 views

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Made easy test series : K-Map
How to solve above question when arrow is added in the Diagram?

asked Jan 21 in Digital Logic by vishal burnwal (135 points) | 23 views

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applied gate: mock dld
The total number of minimal POS expressions present for a K-map having total of 8 minterms out of which 5 are covered by Essential prime implicants while remaining minterms are covered by 3 non essential prime implicant.

asked Jan 21 in Digital Logic by abhinav649 (67 points) | 9 views

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asked Jan 20 in Digital Logic by Chirag Shilwant (180 points) | 15 views

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GATEBOOK MOCK TEST 1 Q49
A sequence detector has to be designed to detect a sequence with at most 3 runs of consecutive zeros of length 3. 001000010001000 This sequence has exactly 2 such runs If we implement a sequential circuit with J-K flip flops then minimum number of flip flops required is ----?

asked Jan 16 in Digital Logic by Rajat Maheshwari (14 points) | 7 views

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ravinder ravula
How to find the characteristic equation of this? [closed]

asked Jan 15 in Digital Logic by meivinay (7 points) | 14 views

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gatebook test sereis: Digital logic
A sequence detector has to be designed to detect a sequence with at most 3 runs of consecutive zeros of length 3. 001000010001000 This sequence has exactly 2 such runs If we implement a sequential circuit with J-K flip flops then minimum number of flip flops required is ----?

asked Jan 15 in Digital Logic by vikas999 (60 points) | 13 views

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fliflops and counters basic doubt
can jhonson counters be implemented using JK flipflop?

asked Jan 15 in Digital Logic by Divyaok (23 points) | 10 views

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ME Test Propagation Delay

asked Jan 14 in Digital Logic by kashyap02 (26 points) | 18 views

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MADE EASY MULTI SUBJECT DIGITAL DOUBT
ANSWER GIVEN IS 6. BUT I AM GETTING ANSWER AS 4. PLEASE CHECK AND CONFIRM.

asked Jan 14 in Digital Logic by SuvasishDutta (209 points) | 23 views

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GATE GURU: WORK BOOK
Binary to Gray Binary to excess 3 Gray to Binary BCD to binary

asked Jan 14 in Digital Logic by Debapaul (699 points) | 18 views

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MADE EASY ADVANCE LEVEL DIGITAL
$\sum m(2,3,6,7)$ $\sum m(0,1,2,3)$ $\sum m(0,1,4,5)$ $\sum m(4,5,6,7)$

answered Jan 13 in Digital Logic by shashin (1.9k points) | 22 views

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MADE EASY FLT: ADVANCE DIGITAL LOGIC
A boolean function $f(A,B,C)=AB’C$ is being implemented using minimum number of $2$ $input$ $NOR$ gates.Each gate is having a propagation delay of $2ns$.What is the overall delay of the circuit? I face a lot of difficulty in solving these types of problems. How to be certain that the circuit u designed contains minimum number of gate?

asked Jan 13 in Digital Logic by Debapaul (699 points) | 34 views

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Self Doubt: Counters
Suppose there is a MOD 6 synchronous counter with 1 AND gate as clearing circuit. If I want to make it MOD 7(ie. count 7 states instead on 6), would I have to introduce a 1 clock delay, or 2 clock delay in the AND gate? Ref: https://gateoverflow.in/151216/digital-electronics-ece-set-3-gate-2016

asked Jan 9 in Digital Logic by Sambhrant Maurya (401 points) | 10 views

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Made Easy Full Length Test 1

answered Jan 9 in Digital Logic by shashin (1.9k points) | 75 views

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Made Easy test series multiple subject digital adder

asked Jan 8 in Digital Logic by Ram Swaroop (270 points) | 15 views

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Self-doubt XOR
How in XOR no of minterms are equal to no of maxterms?

answered Jan 7 in Digital Logic by shashin (1.9k points) | 26 views

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Made easy test series : Number system
Consider a modified 8-bit floating point representation in which 1-bit for sign, 3-bit for exponent and 4-bit for significant. What will be representation for decimal value –12? What is the bias value we have to take for above question?

answered Jan 7 in Digital Logic by yadavg123 (17 points) | 24 views

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