Recent questions tagged cache-memory - GATE CSE Doubts

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Gatebook : CO
What conclusions can be drawn regarding traffic generated to the main memory for write through and write back if we vary miss rate? Higher miss rate write through is superior (generates less traffic) Higher miss rate write back is superior (generates less traffic) Lower miss rate write ... A). 1, 4 are true (B). 2, 3 are true (C). No conclusions can be drawn (D). Similar performance

asked 3 days ago in CO & Architecture by Sambhrant Maurya (271 points) | 11 views

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Gatebook : Memory Organization
Consider a cache system organization employing a line size of 64 Bytes and main memory that requires 40 ns to transfer a 2 Byte word. What is the minimum average number of times a cache line must be made dirty for write-back policy to be more efficient than write-through policy, for any line which is written at-least once?

asked 5 days ago in CO & Architecture by Sambhrant Maurya (271 points) | 7 views

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Gatebook: Memory Organization
The designers of a computer must select a cache system. They have two options. Design #1 uses a direct-mapped cache containing 2 words per cache line. It would have an instruction miss rate of 3% and a data miss rate of 8% Design #2 uses a 2-way set associative cache containing 8 words per cache ... . D1 = 0.70, D2 = 0.40 C. D1 = 0.70, D2 = 0.48 D. D1 = 1.10, D2 = 0.40

asked 5 days ago in CO & Architecture by Sambhrant Maurya (271 points) | 19 views

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Ace subject wise test series CO gate 2019-20
what will be the answer of the below question ?

asked Oct 9 in CO & Architecture by Pratyush Priyam Kuan (72 points) | 26 views

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Gate overflow doubt made easy cache stalls
Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory is 100 cycles.The hit time of L2 cache is 20 cycle.The ... cache is 10 cycles. If there are 2.5 memory references per instruction.How many average stall cycles per instructions are there?

asked Aug 21 in CO & Architecture by Ram Swaroop (75 points) | 13 views

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self doubt-cache memory
Suppose a system has L1,L2,L3 Cache and M as the main memory .now suppose a word W is being searched. the CPU first searches L1 cache whose access time/latency is 10ns .Does not find it. then the CPU again searches L2 cache whose access time is ... word is brought from the main memory to the CPU .is the block containing the word moved simultaneously to the L1,L2,L3 cache?

asked Aug 8 in CO & Architecture by Doraemon (69 points) | 12 views

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Self Doubt - Cache Memory Mapping
Any Good resource to understand Hardware Implementation of various Cache Memory Mapping techniques (Direct, Fully Associative and K-way Set Associative). I mean how many Comparators, Multiplexers, etc. are required? How do they work?

asked Aug 5 in CO & Architecture by ayushsomani (13 points) | 6 views

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OPERATING SYSTEM TLB AND EMAT
Can someone please explain how TLB formula is changed when other concepts like page fault and cache concepts are introduced. There is a lot of confusion and not getting clear explanations. It would be very helpful for every beginners like me. TLB #### EMAT = Ht( t ... also. ( p= page fault rate , PS= pagefault service time, c= cache access time, Hc= hit rate of cache )

asked Aug 5 in Operating System by shankargadri (6 points) | 7 views

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