Recent questions tagged cache-memory - GATE CSE Doubts

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Cache Question Gate
A cache consists of a total of 128 blocks. The main memory contains 2K blocks, each consisting of 32 words. ( I )How many bits are there in each of the TAG, BLOCK and WORD field in case of direct mapping? ( ii )How many bits are there in each of the TAG, SET, and WORD field in case of 4-way set-associative mapping?

asked Apr 24 in CO & Architecture by Beastm0del (7 points) | 5 views

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GATE2017-1-51 Video Solution
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due ... $10$ times. The number of conflict misses experienced by the cache is _________ .

asked Apr 19 in CO & Architecture by admin (3.6k points) | 13 views

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GATE2010-48 Video Solution
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ ... ? $2 \hspace{0.1cm} nanoseconds$ $20 \hspace{0.1cm} nanoseconds$ $22 \hspace{0.1cm}nanoseconds$ $88 \hspace{0.1cm} nanoseconds$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2004-IT-12, ISRO2016-77 Video Solution
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rates of Level $1$ and Level $2$ caches are $0.8$ and $0.9$, respectively. What is the average access time of the system ignoring the search time within the cache? $13.0$ $12.8$ $12.6$ $12.4$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 4 views

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GATE2017-2-45 Video Solution
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: $\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access time (in nanoseconds)}& \text{Hit ratio} \\\hline \text{$ ... fetch and $40$% are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2017-2-29 Video Solution
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is $18$ clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average memory ... respectively are $0.111$ and $0.056$ $0.056$ and $0.111$ $0.0892$ and $0.1784$ $0.1784$ and $0.0892$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2007-80 Video Solution
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ $bytes$ each is used in the system. A $50$ x $50$ two-dimensional array of bytes is stored in the main ... the data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2006-74 Video Solution
Consider two cache organizations. First one is $32 \hspace{0.2cm} KB$ $2-way$ set associative with $32 \hspace{0.2cm} byte$ block size, the second is of same size but direct mapped. The size of an address is $32 \hspace{0.2cm} bits$ in both cases . A $2-to-1$ multiplexer has ... value of $h_1$ is: $2.4 \text{ ns} $ $2.3 \text{ ns}$ $1.8 \text{ ns}$ $1.7 \text{ ns}$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2010-49 Video Solution
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ ... $888 \hspace{0.1cm} \text{nanoseconds}$ $902 \hspace{0.1cm} \text{nanoseconds}$ $968 \hspace{0.1cm} \text{nanoseconds}$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2014-2-9 Video Solution
A $4$-way set-associative cache memory unit with a capacity of $16$ KB is built using a block size of $8$ words. The word length is $32$ bits. The size of the physical address space is $4$ GB. The number of bits for the TAG field is ____

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2014-3-44 Video Solution
The memory access time is $1$ $nanosecond$ for a read operation with a hit in cache, $5$ $nanoseconds$ for a read operation with a miss in cache, $2$ $nanoseconds$ for a write operation with a hit in cache and $10$ $nanoseconds$ for a ... . The cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2017-1-54 Video Solution
A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ____________ bits.

asked Apr 19 in CO & Architecture by admin (3.6k points) | 3 views

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GATE2017-1-25 Video Solution
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2014-1-44 Video Solution
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2008-35 Video Solution
For inclusion to hold between two cache levels $L_1$ and $L_2$ in a multi-level cache hierarchy, which of the following are necessary? $L_1$ must be write-through cache $L_2$ must be a write-through cache The associativity of $L_2$ must be greater than that of $L_1$ The ... be at least as large as the $L_1$ cache IV only I and IV only I, II and IV only I, II, III and IV

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2008-71 Video Solution
Consider a machine with a $2$-way set associative data cache of size $64$ $Kbytes$ and block size $16$ $bytes$. The cache is managed using $32$ $bi$t virtual addresses and the page size is $4$ $Kbytes$. A program to be run on this machine begins as follows: ... $32$ $Kbits$ $34$ $Kbits$ $64$ $Kbits$ $68$ $Kbits$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2014-2-43 Video Solution
In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block size ... size implies a larger cache tag and hence lower cache hit time A smaller block size incurs a lower cache miss penalty

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2016-2-32 Video Solution
The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ KB $8$-way set associative cache is ________ bits.

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2006-41 Video Solution
A CPU has a cache with block size 64 bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive banks with wrap-around. All the $k$ banks can be accessed in parallel, but two ... , the latency of retrieving a cache block starting at address zero from main memory is: 92 ns 104 ns 172 ns 184 ns

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2016-2-50 Video Solution
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $1$ ms and to read a block from the disk is $10$ ms. Assume that the cost of ... are in multiples of $10$ MB. The smallest cache size required to ensure an average read latency of less than $6$ ms is _________ MB.

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2019-1 Video Solution
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated ... $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2012-54 Video Solution
A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ ... bit and $1$ replacement bit. The number of bits in the tag field of an address is $11$ $14$ $16$ $27$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2001-1.7, ISRO2008-18 Video Solution
More than one word are put in one cache block to: exploit the temporal locality of reference in a program exploit the spatial locality of reference in a program reduce the miss penalty none of the above

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2006-80 Video Solution
A CPU has a $32 KB$ direct mapped cache with $128$ byte-block size. Suppose A is two dimensional array of size $512 \times512$ with elements that occupy $8$-bytes each. Consider the following two C code segments, $P1$ and $P2$. P1: for (i=0; i<512; i++) { for (j=0; ... by $P1$ be $M_{1}$and that for $P2$ be $M_{2}$. The value of $M_{1}$ is: $0$ $2048$ $16384$ $262144$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE1992-5-a Video Solution
The access times of the main memory and the Cache memory, in a computer system, are $500$ $n sec$ and $50$ $nsec$, respectively. It is estimated that $80$% of the main memory request are for read the rest for write. The hit ... through policy (where both main and cache memories are updated simultaneously) is used. Determine the average time of the main memory (in ns)

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2013-20 Video Solution
In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are sequenced before the lines in set $(s+1)$. The main memory blocks are numbered 0 onwards. The ... $(j \text{ mod } k) * v \text{ to } (j \text{ mod } k) * v + (v-1) $

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2004-65 Video Solution
Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is: $8, 12, 0, 12, 8$. $2$ $3$ $4$ $5$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2015-2-24 Video Solution
Assume that for a certain processor, a read request takes $50\:\text{nanoseconds}$ on a cache miss and $5\:\text{nanoseconds}$ on a cache hit. Suppose while running a program, it was observed that $80\%$ of the processor's read requests result in a cache hit. The average read access time in nanoseconds is ______.

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2008-72 Video Solution
Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR[1024][1024]; int i, ... the same cache index as $ARR[0][0]$? $ARR[0][4]$ $ARR[4][0]$ $ARR[0][5]$ $ARR[5][0]$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2005-67 Video Solution
Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and the number of tag bits are respectively, $10, 17$ $10, 22$ $15, 17$ $5, 17$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2009-29 Video Solution
Consider a $4$-way set associative cache (initially empty) with total $16$ cache blocks. The main memory consists of $256$ ... $3$ $8$ $129$ $216$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE1990-7a Video Solution
A block-set associative cache memory consists of $128$ blocks divided into four block sets. The main memory consists of $16, 384$ blocks and each block contains $256$ eight bit words. How many bits are required for addressing the main memory? How many bits are needed to represent the TAG, SET and WORD fields?

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2011-43 Video Solution
An $8KB$ direct-mapped write-back cache is organized as multiple blocks, each size of $32$-$bytes$. The processor generates $32$-$bit$ addresses. The cache controller contains the tag information for each cache block comprising of the following. $1$ valid bit $1$ modified ... to store meta-data (tags) for the cache? $4864$ $bits$ $6144$ $bits$ $6656$ $bits$ $5376$ $bits$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2019-45 Video Solution
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept ... for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE1996-26 Video Solution
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below: $\overset{ \text {Level $1$ (Cache memory)} \\ \text{Access time = $ ... of less than $100 nsec$? What is the average access time achieved using the chosen sizes of level $1$ and level $2$ memories?

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2001-9 Video Solution
A CPU has $32-bit$ memory address and a $256 \ KB$ cache memory. The cache is organized as a $4-way$ set associative cache with cache block size of $16$ bytes. What is the number of sets in the cache? What is the size (in bits) of ... are required to find the byte offset within a cache block? What is the total amount of extra memory (in bytes) required for the tag bits?

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2004-IT-48 Video Solution
Consider a fully associative cache with $8$ cache blocks (numbered $0-7$) and the following sequence of memory block requests: $4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7$ If LRU replacement policy is used, which cache block will have memory block $7$? $4$ $5$ $6$ $7$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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GATE2017-2-53 Video Solution
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is _______

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2006-75 Video Solution
Consider two cache organizations. First one is $32$ $kB$ $2$-way set associative with $32$ $byte$ block size, the second is of same size but direct mapped. The size of an address is $32$ $bits$ in both cases . A $2$-to-$1$ multiplexer has latency of $0.6 ns$ while a $k-$bit ... of direct mapped is $h_2$. The value of $h_2$ is: $2.4$ $ns$ $2.3$ $ns$ $1.8$ $ns$ $1.7$ $ns$

asked Apr 19 in CO & Architecture by admin (3.6k points) | 1 view

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GATE2014-2-44 Video Solution
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected? Width of tag comparator Width of set index decoder Width of way selection multiplexer Width of processor to main memory data bus

asked Apr 19 in CO & Architecture by admin (3.6k points) | 2 views

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