Recent questions tagged cache-memory - GATE CSE Doubts

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Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

asked Mar 21 in CO & Architecture by smsubham (64 points) | 14 views

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Made Easy test series coa cache memory ft6
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4-way set associative LRU cache is used is ________. (Upto 1 decimal places) 100, 104, 108, 104, 107, 108, 105, 102, 108, 103

asked Jan 22 in CO & Architecture by Ram Swaroop (270 points) | 9 views

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Made Easy test series coa cache memory ft 3 cpi
Consider a CPU that executes at a clock rate of 200 MHz (5 ns per cycle) with a single level of cache. CPIexecution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% arithmetic/logical, 30% load/store, 20% control ... of 5 cycles. The number of times cpu with ideal memory is faster when no miss-occurs _______. (Upto 2 decimal places)

asked Jan 21 in CO & Architecture by Ram Swaroop (270 points) | 14 views

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Cache Question
Consider a single level cache with an access time of 6 ns, line size of 64 bytes and the hit ratio of 0.8. Main memory uses a block transfer capability that has a first word (8 bytes) access time of 40 ns and 15 ns for each word there after. ... cache miss? (Assume that the cache waits until the line has been fetched from main memory and re executes for a hit) Anyone please clarify.

asked Jan 21 in CO & Architecture by Shivateja MST (113 points) | 6 views

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Made Easy test series coa cache memory t2 16
Suppose that a processor has access to three levels of memory. Level 1 contain 2000 words and has an access time of 0.02 msec. Level 2 contain 10,000 words and has an access time of 0.2 msec. Level 3 contains 20,000 words and has an access time ... The hit ratio for level 1 is 0.65 and for level 2 is 0.45. The average access time (in μsec) is ________.

asked Jan 17 in CO & Architecture by Ram Swaroop (270 points) | 44 views

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Made Easy test series coa cache mapping single subject 33

asked Jan 17 in CO & Architecture by Ram Swaroop (270 points) | 35 views

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Average memory access time of cache
For this question, they've solved it using the formula AMAT = H1T1 + M1(H2T2 + M2 ...) and so on. However, since the question has directly given the hit time of the cache, I thought it'd be more appropriate to use the formula: ... ) + MissRate(MM)*(HitTime(Secondary))) So, which one is more appropriate and how would you differentiate between the two use cases?

asked Jan 17 in CO & Architecture by goxul (377 points) | 16 views

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Made Easy test series coa cache memory access time

asked Jan 16 in CO & Architecture by Ram Swaroop (270 points) | 30 views

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Made Easy Cache memory
Consider the cache memory that is 30 times faster than main memory and used 90% of the total time. What is the speedup gain by the cache memory?

asked Jan 12 in CO & Architecture by Deterministic (12 points) | 28 views

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Computer organization made easy test series

asked Jan 1 in CO & Architecture by Chirag Shilwant (180 points) | 28 views

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MADE EASY TEST SERIES Memory Access Time
Consider a cache memory which is 30 times faster than main memory and it can be used 90% of the time. Speed up gained by the cache memory is ____.

asked Dec 28, 2019 in CO & Architecture by tamaldeepmaity (17 points) | 64 views

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Self Doubt in https://gateoverflow.in/131040/test-by-bikram-2017-computer-architecture-test-2-29

asked Dec 26, 2019 in CO & Architecture by Sambhrant Maurya (401 points) | 25 views

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ACe topic wise test CO Q14

asked Dec 24, 2019 in CO & Architecture by ssap09 (42 points) | 12 views

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Madeeasy computerorganization test series
Can someone please give solution to this problem Thank you

asked Nov 30, 2019 in CO & Architecture by Pratyush Priyam Kuan (804 points) | 9 views

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nptel Assignment :CO and Architecture
Consider a two-level memory hierarchy with separate instruction and data caches in level 1, and main memory in level 2. The clock cycle time in 1 ns. The miss penalty is 20 clock cycles for both read and write. 2% of the instructions ... clock cycle. The average access time of the memory hierarchy will be . nanoseconds. Can anyone plz provide the solution.

asked Nov 21, 2019 in CO & Architecture by vishal burnwal (135 points) | 24 views

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Average Access Time of Read on Cache Hit and Cache Miss

asked Nov 14, 2019 in CO & Architecture by goxul (377 points) | 28 views

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virtually indexed physically tagged cache
Can someone please explain the concept behind virtually indexed and physically tagged cache ?

asked Nov 10, 2019 in Operating System by Pratyush Priyam Kuan (804 points) | 10 views

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Gatebook : CO
What conclusions can be drawn regarding traffic generated to the main memory for write through and write back if we vary miss rate? Higher miss rate write through is superior (generates less traffic) Higher miss rate write back is superior (generates less traffic) Lower miss rate write ... A). 1, 4 are true (B). 2, 3 are true (C). No conclusions can be drawn (D). Similar performance

asked Oct 19, 2019 in CO & Architecture by Sambhrant Maurya (401 points) | 15 views

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Gatebook : Memory Organization
Consider a cache system organization employing a line size of 64 Bytes and main memory that requires 40 ns to transfer a 2 Byte word. What is the minimum average number of times a cache line must be made dirty for write-back policy to be more efficient than write-through policy, for any line which is written at-least once?

asked Oct 17, 2019 in CO & Architecture by Sambhrant Maurya (401 points) | 11 views

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Gatebook: Memory Organization
The designers of a computer must select a cache system. They have two options. Design #1 uses a direct-mapped cache containing 2 words per cache line. It would have an instruction miss rate of 3% and a data miss rate of 8% Design #2 uses a 2-way set associative cache containing 8 words per cache ... . D1 = 0.70, D2 = 0.40 C. D1 = 0.70, D2 = 0.48 D. D1 = 1.10, D2 = 0.40

asked Oct 17, 2019 in CO & Architecture by Sambhrant Maurya (401 points) | 33 views

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Ace subject wise test series CO gate 2019-20
what will be the answer of the below question ?

asked Oct 9, 2019 in CO & Architecture by Pratyush Priyam Kuan (804 points) | 33 views

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Gate overflow doubt made easy cache stalls
Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory is 100 cycles.The hit time of L2 cache is 20 cycle.The ... cache is 10 cycles. If there are 2.5 memory references per instruction.How many average stall cycles per instructions are there?

asked Aug 21, 2019 in CO & Architecture by Ram Swaroop (270 points) | 19 views

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self doubt-cache memory
Suppose a system has L1,L2,L3 Cache and M as the main memory .now suppose a word W is being searched. the CPU first searches L1 cache whose access time/latency is 10ns .Does not find it. then the CPU again searches L2 cache whose access time is ... word is brought from the main memory to the CPU .is the block containing the word moved simultaneously to the L1,L2,L3 cache?

asked Aug 8, 2019 in CO & Architecture by Doraemon (99 points) | 15 views

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Self Doubt - Cache Memory Mapping
Any Good resource to understand Hardware Implementation of various Cache Memory Mapping techniques (Direct, Fully Associative and K-way Set Associative). I mean how many Comparators, Multiplexers, etc. are required? How do they work?

asked Aug 5, 2019 in CO & Architecture by ayushsomani (13 points) | 7 views

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OPERATING SYSTEM TLB AND EMAT
Can someone please explain how TLB formula is changed when other concepts like page fault and cache concepts are introduced. There is a lot of confusion and not getting clear explanations. It would be very helpful for every beginners like me. TLB #### EMAT = Ht( t ... also. ( p= page fault rate , PS= pagefault service time, c= cache access time, Hc= hit rate of cache )

asked Aug 5, 2019 in Operating System by shankargadri (8 points) | 8 views

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