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Recent questions tagged cache-memory
0
votes
1
answer
44
views
A 32-bit wide memory has a 22-bit address to be accessed. What is the maximum memory capacity in MB?
AniruddhaSaha
asked
in
CO & Architecture
Feb 24
by
AniruddhaSaha
5
points
44
views
cache-memory
0
votes
0
answers
46
views
#Madeeasy #COA #page-replacement #cache-memory
Consider a direct mapped cache with 16 blocks with block size of 16 bytes. Initially the cache is empty. The following sequence of access of memory blocks: Ox80000, Ox80008, Ox80010, Ox80018, Ox30010 is repeated 10 times. Which of the following represents ... = 3 and conflict = 18 C.Compulsory = 4 and conflict = 16 D.Compulsory = 2 and conflict = 20
Abhishek tarpara
asked
in
CO & Architecture
Sep 4, 2021
by
Abhishek tarpara
13
points
46
views
made-easy-test-series
co-and-architecture
page-replacement
cache-memory
0
votes
1
answer
35
views
Unacademy Navigate (CS&IT) Question no. 26
The value represented by the following 32-bits in IEEE-754 standard is? 0100000111100000……00
Jagat_Jyoti
asked
in
CO & Architecture
May 27, 2021
by
Jagat_Jyoti
5
points
35
views
cache-memory
0
votes
0
answers
60
views
In a computer system, the cache memory uses two-way set associative mapping technique to do the address translation.
Aman Patel
asked
in
CO & Architecture
Apr 2, 2021
by
Aman Patel
5
points
60
views
cache-memory
3
votes
3
answers
909
views
GATE CSE 2021 Set 2 | Question: 19 | Video Solution
Arjun
asked
in
CO & Architecture
Feb 18, 2021
by
Arjun
1.4k
points
909
views
gate2021-cse-set2
numerical-answers
co-and-architecture
cache-memory
1
vote
0
answers
720
views
GATE CSE 2021 Set 2 | Question: 27 | Video Solution
Arjun
asked
in
CO & Architecture
Feb 18, 2021
by
Arjun
1.4k
points
720
views
gate2021-cse-set2
co-and-architecture
cache-memory
multilevel-cache
0
votes
3
answers
448
views
GATE CSE 2021 Set 1 | Question: 22 | Video Solution
Arjun
asked
in
CO & Architecture
Feb 18, 2021
by
Arjun
1.4k
points
448
views
gate2021-cse-set1
co-and-architecture
cache-memory
numerical-answers
0
votes
0
answers
31
views
Where to read Cache Memory concept ?
Hi, my concepts regarding cache memory is weak. Please let me know that where (book or online source) to read Cache memory concepts ? If you have any knowledge about it please share ? Please try to share only standard sources.
beta
asked
in
CO & Architecture
Feb 17, 2021
by
beta
5
points
31
views
cache-memory
self-doubt
1
vote
0
answers
43
views
why pagetables are not present in cache memory?
pradeep jagarlamudi
asked
in
Operating System
Jan 22, 2021
by
pradeep jagarlamudi
9
points
43
views
cache-memory
0
votes
1
answer
42
views
Ace Subject Wise Test CO
Raj Bopche
asked
in
CO & Architecture
Jan 3, 2021
by
Raj Bopche
13
points
42
views
cache-memory
1
vote
0
answers
59
views
Self Doubt - Amdahl's Law in Cache Organisation
Is Amdahl's Law applicable in a system having Cache and Main Memory in Hierarchical Organization or is it limited to Simultaneous Organization only. The Effective Memory Access Time of system having Simultaneous Organization matches the time predicted by Amdahl's Law but not so in the case of Hierarchical Organization. Am I doing something wrong?
shantanu4raje
asked
in
CO & Architecture
Nov 6, 2020
by
shantanu4raje
25
points
59
views
cache-memory
self-doubt
syllabus-doubt
0
votes
1
answer
77
views
Made Easy Test Series
What would be the answer? I am getting 100.
Sinchit
asked
in
CO & Architecture
Oct 16, 2020
by
Sinchit
17
points
77
views
cache-memory
0
votes
1
answer
98
views
Made Easy, COA Subject wise test 2 | Cache Memory
A cache has a hit time of 10ns and hit rate of 60%. An optimization was made to increase the hit rate to 70%, but the hit time also got increased to 15ns. The optimization resulted in 10% reduction in average memory access time. Assume that the miss penalty is unaffected by the optimization. The miss penalty of the cache (in ns) is___?
Animesh Sinha
asked
in
CO & Architecture
Sep 9, 2020
by
Animesh Sinha
25
points
98
views
cache-memory
3
votes
2
answers
539
views
COA made easy test series question on Cache memory mapping
ijnuhb
asked
in
CO & Architecture
Sep 2, 2020
by
ijnuhb
751
points
539
views
made-easy-test-series
computer-architecture
cache-memory
computer-organisation-and-architechture
0
votes
1
answer
71
views
Virtual Memory | OS
Is there any good resources for Virtual Memory because i’m not able to do the question based on calculating effective memory access time in case of page fault,tlb miss and cache miss ?
kaleen bhaiya
asked
in
Operating System
Sep 2, 2020
by
kaleen bhaiya
9
points
71
views
operating-system
memory-management
operating-system
cache-memory
0
votes
2
answers
48
views
#OS Memory management question from Made Easy Handbook
dhruvikk6
asked
in
Operating System
Aug 29, 2020
by
dhruvikk6
5
points
48
views
operating-system
memory-management
cache-memory
effective-memory-access-time
0
votes
0
answers
116
views
Computers organization
As an important part of CPU, ALU supports the functionality of Performing many different functions, Can you elaborate on this statement by showing an example of one addition and one AND operation in 4 bit registers over the given hardware. Give the set of selection that will be required to perform this action.
Ojesh Bhagat
asked
in
CO & Architecture
Aug 27, 2020
by
Ojesh Bhagat
5
points
116
views
co-and-architecture
cache-memory
capacity-miss
0
votes
0
answers
18
views
#capacity miss #caching #misses #computer organization
prakhar123
asked
in
CO & Architecture
Aug 2, 2020
by
prakhar123
7
points
18
views
co-and-architecture
cache-memory
capacity-miss
0
votes
0
answers
50
views
computer organization(architecture) question
A computer system has 64KB main memory and 1KB data cache memory. Data transfer between cache and main memory is done using 16 * 8 blocks. The set associative method, which includes 2 blocks in each set (set), is used. LRU (Least ... in the first accesses. During the running of the program, you can show and transfer data between main memory and cache.
helixum
asked
in
CO & Architecture
Jun 12, 2020
by
helixum
5
points
50
views
co-and-architecture
pipelining
cache-memory
0
votes
0
answers
32
views
made easy wb
how to solve questions like this, I got this TAG SETS WORDS 18 7 7
ummokkate
asked
in
CO & Architecture
Jun 5, 2020
by
ummokkate
33
points
32
views
co-and-architecture
cache-memory
0
votes
1
answer
173
views
Computer Organization And Embedded Systems Sixth Edition by Carl Hamacher Chapter 1, Problem no. 1.5, Page no. 25.
Gaurav Padole
asked
in
CO & Architecture
May 16, 2020
by
Gaurav Padole
5
points
173
views
co-and-architecture
cache-memory
0
votes
1
answer
52
views
Self Doubt from COA
What would happen if we keep increasing the levels of cache, like 2 level cache is more efficient than 1 level cache so why can’t we have 20 level cache? How will it impact performance . Kindly cite the source for your answer
anurag sharma
asked
in
CO & Architecture
May 12, 2020
by
anurag sharma
83
points
52
views
co-and-architecture
cache-memory
2
votes
0
answers
289
views
Cache Question Gate
A cache consists of a total of 128 blocks. The main memory contains 2K blocks, each consisting of 32 words. ( I )How many bits are there in each of the TAG, BLOCK and WORD field in case of direct mapping? ( ii )How many bits are there in each of the TAG, SET, and WORD field in case of 4-way set-associative mapping?
Beastm0del
asked
in
CO & Architecture
Apr 23, 2020
by
Beastm0del
13
points
289
views
co-and-architecture
computer-architecture
cache-memory
0
votes
1
answer
96
views
GATE2017-1-51 Video Solution
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due ... $10$ times. The number of conflict misses experienced by the cache is _________ .
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
96
views
gate2017-1
co-and-architecture
cache-memory
conflict-misses
normal
numerical-answers
video-solution
0
votes
0
answers
27
views
GATE2010-48 Video Solution
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ ... ? $2 \hspace{0.1cm} nanoseconds$ $20 \hspace{0.1cm} nanoseconds$ $22 \hspace{0.1cm}nanoseconds$ $88 \hspace{0.1cm} nanoseconds$
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
27
views
gate2010
co-and-architecture
cache-memory
normal
barc2017
video-solution
0
votes
0
answers
26
views
GATE2004-IT-12, ISRO2016-77 Video Solution
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rates of Level $1$ and Level $2$ caches are $0.8$ and $0.9$, respectively. What is the average access time of the system ignoring the search time within the cache? $13.0$ $12.8$ $12.6$ $12.4$
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
26
views
gate2004-it
co-and-architecture
cache-memory
normal
isro2016
video-solution
0
votes
0
answers
18
views
GATE2017-2-45 Video Solution
The read access times and the hit ratios for different caches in a memory hierarchy are as given below: $\begin{array}{|l|c|c|} \hline \text {Cache} & \text{Read access time (in nanoseconds)}& \text{Hit ratio} \\\hline \text{$ ... fetch and $40$% are for memory operand fetch. The average read access time in nanoseconds (up to $2$ decimal places) is _________
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
18
views
gate2017-2
co-and-architecture
cache-memory
numerical-answers
video-solution
0
votes
0
answers
20
views
GATE2017-2-29 Video Solution
In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is $18$ clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average memory ... respectively are $0.111$ and $0.056$ $0.056$ and $0.111$ $0.0892$ and $0.1784$ $0.1784$ and $0.0892$
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
20
views
gate2017-2
cache-memory
co-and-architecture
normal
video-solution
0
votes
0
answers
71
views
GATE2007-80 Video Solution
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ $bytes$ each is used in the system. A $50$ x $50$ two-dimensional array of bytes is stored in the main ... the data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
71
views
gate2007
co-and-architecture
cache-memory
normal
video-solution
0
votes
0
answers
21
views
GATE2006-74 Video Solution
Consider two cache organizations. First one is $32 \hspace{0.2cm} KB$ $2-way$ set associative with $32 \hspace{0.2cm} byte$ block size, the second is of same size but direct mapped. The size of an address is $32 \hspace{0.2cm} bits$ in both cases . A $2-to-1$ multiplexer has ... value of $h_1$ is: $2.4 \text{ ns} $ $2.3 \text{ ns}$ $1.8 \text{ ns}$ $1.7 \text{ ns}$
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
21
views
gate2006
co-and-architecture
cache-memory
normal
video-solution
0
votes
0
answers
13
views
GATE2010-49 Video Solution
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ ... $888 \hspace{0.1cm} \text{nanoseconds}$ $902 \hspace{0.1cm} \text{nanoseconds}$ $968 \hspace{0.1cm} \text{nanoseconds}$
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
13
views
gate2010
co-and-architecture
cache-memory
normal
video-solution
0
votes
0
answers
32
views
GATE2014-2-9 Video Solution
A $4$-way set-associative cache memory unit with a capacity of $16$ KB is built using a block size of $8$ words. The word length is $32$ bits. The size of the physical address space is $4$ GB. The number of bits for the TAG field is ____
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
32
views
gate2014-2
co-and-architecture
cache-memory
numerical-answers
normal
video-solution
0
votes
0
answers
19
views
GATE2014-3-44 Video Solution
The memory access time is $1$ $nanosecond$ for a read operation with a hit in cache, $5$ $nanoseconds$ for a read operation with a miss in cache, $2$ $nanoseconds$ for a write operation with a hit in cache and $10$ $nanoseconds$ for a ... . The cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
19
views
gate2014-3
co-and-architecture
cache-memory
numerical-answers
normal
video-solution
0
votes
0
answers
23
views
GATE2017-1-54 Video Solution
A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ____________ bits.
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
23
views
gate2017-1
co-and-architecture
cache-memory
normal
numerical-answers
video-solution
0
votes
0
answers
24
views
GATE2017-1-25 Video Solution
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
24
views
gate2017-1
co-and-architecture
cache-memory
numerical-answers
video-solution
0
votes
0
answers
20
views
GATE2014-1-44 Video Solution
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
20
views
gate2014-1
co-and-architecture
cache-memory
normal
video-solution
0
votes
0
answers
18
views
GATE2008-35 Video Solution
For inclusion to hold between two cache levels $L_1$ and $L_2$ in a multi-level cache hierarchy, which of the following are necessary? $L_1$ must be write-through cache $L_2$ must be a write-through cache The associativity of $L_2$ must be greater than that of $L_1$ The ... be at least as large as the $L_1$ cache IV only I and IV only I, II and IV only I, II, III and IV
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
18
views
gate2008
co-and-architecture
cache-memory
normal
video-solution
0
votes
0
answers
18
views
GATE2008-71 Video Solution
Consider a machine with a $2$-way set associative data cache of size $64$ $Kbytes$ and block size $16$ $bytes$. The cache is managed using $32$ $bi$t virtual addresses and the page size is $4$ $Kbytes$. A program to be run on this machine begins as follows: ... $32$ $Kbits$ $34$ $Kbits$ $64$ $Kbits$ $68$ $Kbits$
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
18
views
gate2008
co-and-architecture
cache-memory
normal
video-solution
0
votes
0
answers
16
views
GATE2014-2-43 Video Solution
In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block size ... size implies a larger cache tag and hence lower cache hit time A smaller block size incurs a lower cache miss penalty
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
16
views
gate2014-2
co-and-architecture
cache-memory
normal
video-solution
0
votes
0
answers
24
views
GATE2016-2-32 Video Solution
The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ KB $8$-way set associative cache is ________ bits.
admin
asked
in
CO & Architecture
Apr 18, 2020
by
admin
585
points
24
views
gate2016-2
co-and-architecture
cache-memory
normal
numerical-answers
video-solution
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