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Welcome to GATE CSE Doubts, where you can ask questions and receive answers from other members of the community.

Recent questions tagged co-and-architecture

0 votes
1 answer 10 views
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown : What is the number of cycles needed to execute the following loop? for (i = 1; i < = 1000; i++) {I1, I2, I3, I4}
asked Jul 22 in CO & Architecture swami_9 5 points 10 views
0 votes
2 answers 40 views
Can anyone give link of PDF of gate CS questions with solutions for the subject Digital Logic only if available. I only need one subject as it is common with Electrical... Digital Logic only if available ... 1. https://www.youtube.com/playlist?list= ... V9rs 5. https://www.cs.cornell.edu/~tomf/notes/cps104/twoscomp.html https://drive.google.com/file/d/0Byt7-j-JD0d0bmxlRkZGcjN2cjA/view
asked Jul 22 in GATE asqwer 633 points 40 views
0 votes
1 answer 21 views
A byte addressable computer has a small data cache capable of holding sixteen 32 bit words. Each cache block consist of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4 way set associative LRU cache is used is ________. (Upto 1 decimal places) 100, 104, 108, 104, 107, 108, 105, 102, 108, 103
asked Jul 18 in CO & Architecture Abhishek tarpara 13 points 21 views
0 votes
1 answer 12 views
A computer system with a word length of 32 bits has a 16 MB word- addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation. A1 = 0x42C8A4, A2 = 0x546888, ... the same cache set. C A3 and A4 are mapped to the same cache set. D A1 and A3 are mapped to the same cache set.
asked Jul 14 in CO & Architecture swami_9 5 points 12 views
0 votes
1 answer 13 views
“Stack pointer is decremented locally” What does this mean? This was present in one of the previous year gate question on topic control unit design
asked Jul 13 in CO & Architecture Harshad_Shinde 5 points 13 views
0 votes
1 answer 29 views
Determine the width of Micro-instruction having following Control signal field, in a Vertical Microprogrammed Control Unit 1. Next Address field of 7 Bits 2. ALU Function field selecting 1 out of 13 ALU Function. 3. Register-in field selecting 1 out of 13 ALU Function. 4. Register-out field ... no shift, right shift or left shift. 6. Auxiliary control field of 4 bits. (a) 22 (b) 23 (c)24 (d) 25
asked Jul 8 in CO & Architecture Ranjul Bandyopadhyay 7 points 29 views
0 votes
1 answer 187 views
I am making a list of different types of numericals that can possibly come in GATE from different subjects .. This list is not comprehensive, so please ... ?fbclid=IwAR0ezzTYvJdobF2hXtr3xVNZpZOFtw96yHAywR2_j9BOKGe1mBNSgVUcsvw#9xiori58gq22i 7. https://www.mediafire.com/folder/gp6z7khjzyl8d/gate_materials?fbclid=IwAR0ezzTYvJdobF2hXtr3xVNZpZOFtw96yHAywR2_j9BOKGe1mBNSgVUcsvw#mp3qyi2prh3fb
asked Jul 5 in Others asqwer 633 points 187 views
3 votes
3 answers 899 views
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________
asked Feb 18 in CO & Architecture Arjun 1.5k points 899 views
2 votes
1 answer 1K views
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ processor. If $0.5 \%$ processor cycles are used for $\text{DMA}$, the data transfer rate of the device is __________ bits per second.
asked Feb 18 in CO & Architecture Arjun 1.5k points 1K views
1 vote
0 answers 713 views
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write allocate policy must be ... $S_2$ is false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false
asked Feb 18 in CO & Architecture Arjun 1.5k points 713 views
5 votes
2 answers 1.3K views
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
asked Feb 18 in CO & Architecture Arjun 1.5k points 1.3K views
0 votes
3 answers 443 views
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.
asked Feb 18 in CO & Architecture Arjun 1.5k points 443 views
1 vote
2 answers 526 views
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.
asked Feb 18 in CO & Architecture Arjun 1.5k points 526 views
2 votes
2 answers 799 views
Consider the following instruction sequence where registers $R1, R2$ and $R3$ are general purpose and $\text{MEMORY}[X]$ denotes the content at the memory location $X$ ... format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________
asked Feb 18 in CO & Architecture Arjun 1.5k points 799 views
0 votes
0 answers 24 views
What is the meaning of Branch folding in pipelining?
asked Sep 7, 2020 in CO & Architecture nvs16 9 points 24 views
0 votes
1 answer 54 views
I am not able to understand this particular line. As to how it will work.: “conversely if there is an delay in fetching instructions because of a branch or a cache miss the dispatch unit continues to issue instructions from the instruction queue” It is in Carl Hamacher Pipelining chapter. Link. If anyone could explain it using a timeline diagram it would be great. I am not able to visualize it.
asked Sep 7, 2020 in CO & Architecture nvs16 9 points 54 views
0 votes
0 answers 66 views
A program consisting of 12 instructions I1, I2, ..., I12 is executed in the pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. What are the number of clock cycles if the stages are IF, ID, EX, MA, WB and each stage takes 1cc
asked Sep 7, 2020 in CO & Architecture ijnuhb 747 points 66 views
0 votes
0 answers 115 views
Consider the instruction set architecture of a general-purpose machine. Suppose that a total of 20 control signals are present, out of which 7 are mutually exclusive while the rest are not. The number of bits required in the control word (for microprogramming) will beat least
asked Sep 7, 2020 in CO & Architecture ijnuhb 747 points 115 views
0 votes
1 answer 44 views
Consider the type addressable memory unit of a computer has 64 K words of 16 bit each. The computer has an instruction format with 4 fields namely opcode, mode field specify 9-addressing modes, register address field with 50 registers and a memory address field. If an instruction is 32 bits long then the number of different instructions are
asked Sep 6, 2020 in CO & Architecture Scion_of_fire 49 points 44 views
0 votes
1 answer 180 views
Which of the following is not involved in a memory write operation? a) MAR b) PC c) MDR d) Data bus
asked Sep 6, 2020 in CO & Architecture himali15 5 points 180 views
0 votes
1 answer 31 views
A 2 ns clock cycle processors consumes 4 cycles for ALU operations, 3 cycles for branches and 5 cycles for memory operations. The relative frequencies of these operations are 45%, 15% and 40% respectively. Q.16 What is the average instruction execution time (in nano ... 17 What is performance in MIPS? Q.18 If the program contains 10 instructions. What is the program execution time (in sec)?
asked Sep 5, 2020 in CO & Architecture Scion_of_fire 49 points 31 views
0 votes
1 answer 26 views
The stage delays in a 4-stage pipeline are 800,500,400 and 300picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays 600 and 350picoseconds. The throughput increase of the pipeline is ___________ percent. Just posting my approach towards this problem
asked Aug 29, 2020 in CO & Architecture ijnuhb 747 points 26 views
0 votes
0 answers 47 views
As an important part of CPU, ALU supports the functionality of Performing many different functions, Can you elaborate on this statement by showing an example of one addition and one AND operation in 4 bit registers over the given hardware. Give the set of selection that will be required to perform this action.
asked Aug 27, 2020 in CO & Architecture Ojesh Bhagat 5 points 47 views
0 votes
2 answers 50 views
What are some good resources for pipelining in COA portion ? Is Hamacher sufficient ?
asked Aug 27, 2020 in CO & Architecture Arkaprava 867 points 50 views
1 vote
0 answers 59 views
how to solve such question when interrupt service time is greater than transfer time??
asked Aug 26, 2020 in CO & Architecture abcd9982 87 points 59 views
0 votes
1 answer 40 views
ALU instruction in a RISC instruction pipeline will not have any operation in MEM stage of pipeline is this statement true because ALU operations in RISC do not use memory access (like load/store)??
asked Aug 20, 2020 in CO & Architecture abcd9982 87 points 40 views
2 votes
0 answers 37 views
I want to ask that IR contains the instruction but for fetching that instruction we need a set of micro-operations which are present inside the control memory and only after executing those micro-operations we are able to perform fetch. So what does IR contain initially? ... from memory, so where is the micro-program that is written for the fetch present.$??$ Please someone provide a explanation.
asked Aug 19, 2020 in CO & Architecture KUSHAGRA गुप्ता 1.4k points 37 views
0 votes
0 answers 70 views
In the above question the answer is given as C but I am not understanding why it is not B. Can someone explain with reference?
asked Aug 15, 2020 in CO & Architecture Mellophi 363 points 70 views
0 votes
0 answers 26 views
source : https://gateoverflow.in/204126/gate2018-51 In the answer part given by arjun sir he is trying to say that there are $2^{16}$ instruction encodings. What are these? How to think that we have to consider encodings and not the instructions after reading the question?
asked Aug 9, 2020 in CO & Architecture KUSHAGRA गुप्ता 1.4k points 26 views
0 votes
0 answers 29 views
Source : https://gateoverflow.in/2590/gate1995-1-3 In this question the answer given as B. How? Vectored interrupts like RST 7.5, RST 6.5 etc and the ISR for each one of them is stored in the IVT and if I go to the IVT there I will find a address ... ISR is present. So is it not the answer should be A. I think B option clearly tells us about non-vectored interrupts. Please someone clarify this.
asked Aug 9, 2020 in CO & Architecture KUSHAGRA गुप्ता 1.4k points 29 views
0 votes
1 answer 20 views
DO most(if not all) caches implement temporal locality of reference? Any examples where spatial locality of reference is used?
asked Aug 5, 2020 in CO & Architecture nvs16 9 points 20 views
0 votes
1 answer 29 views
Source : https://gateoverflow.in/1063/gate2004-69 In this question we have gate delays, latch delays and 1000 inst. and arjun sir's answer make it very clear on how to proceed without making use of any formula. Source : https://gateoverflow.in/330/gate2013-45 But if ... I am applying the same logic as above question I am getting answer as 164 instead of directly multiplying 15*11. Why is that $?$
asked Aug 5, 2020 in CO & Architecture KUSHAGRA गुप्ता 1.4k points 29 views
0 votes
0 answers 22 views
If there is a miss in L1 cache then a block of size same as that in L1 is brought back to the L1 cache irrespective of the block size of L2 cache or memory. Is this statement correct?
asked Aug 2, 2020 in CO & Architecture Mellophi 363 points 22 views
0 votes
0 answers 12 views
CAN WE HAVE MORE THAN ONE CAPACITY MISS FOR THE SAME BLOCK NUMBER ? WHICH MEANS LET SAY WE HAVE A SEQUENCE OF BLOCK NUMBER ARE :- 0,5,2,7,4,0,4,0 AND NO OF LINES/BLOCK IN CACHE ARE 4, THEN WILL 3RD ACCESS TO BLOCK 0(LAST BLOCK) CAPACITY MISS OR CONFLICT MISS? IF IT IS CONFLICT MISS, THEN IN WHAT ACCESS SEQUENCE WE WILL GET THE 3RD ACCESS TO ZERO BLOCK AS CAPACITY MISS ?
asked Aug 2, 2020 in CO & Architecture prakhar123 7 points 12 views
0 votes
0 answers 13 views
In write through cache if the hit ratio for write is given as 1 then do we consider both write and read as simultaneous or just write as simultaneous and read as hierarchal? Please provide the reference also.
asked Aug 1, 2020 in CO & Architecture Mellophi 363 points 13 views
0 votes
0 answers 18 views
In this question Arjun sir has used operand forwarding from EX in I3 to EX in I4. Instead, can we think of it like split phase between EX in I3 to ID in I4? https://gateoverflow.in/34735/madeeasy-test-series-co-%26-architecture-pipelining
asked Jul 7, 2020 in CO & Architecture pranavsettaluri9 5 points 18 views
0 votes
0 answers 39 views
Consider 2 MBPS I/O device interfaced to 64 bit CPU in a programmed-I/O mode. Data transmission between the CPU and I/O in word-wise. Interrupt overhead is 3 μ/sec. What is the performance gain when the device is operating under interrup-I/O over programmed-I/O mode? A)2 B)2.5 C)1.33 D)2.66
asked Jul 1, 2020 in CO & Architecture arpit_18 5 points 39 views
0 votes
0 answers 16 views
We are having a five-stage RISC architecture pipeline where the stages are instruction fetch ->decode->execute->memory access->write back, in which we are executing a single instruction ADD R1,R2,R3. As we can see that this instruction doesn’t require a memory access stage then the total number of cycles required to execute this single instruction is 4 cycles or 5 cycles?
asked Jul 1, 2020 in CO & Architecture bittujash 5 points 16 views
0 votes
1 answer 45 views
Kindly explained this in detailed way, like why particular steps will come and reason behind it.
asked Jul 1, 2020 in CO & Architecture prakhar123 7 points 45 views
0 votes
1 answer 136 views
Consider the type addressable memory unit of a computer has 64 K words of 16 bit each. The computer has an instruction format with 4 fields namely opcode, mode field specify 9-addressing modes, register address field with 50 registers and a memory address field. If an instruction is 32 bits long then the number of different instructions are _____.
asked Jun 25, 2020 in CO & Architecture arpit_18 5 points 136 views
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