# Recent questions tagged computer-architecture

Suppose our computer requires 2048x16 bytes of RAM and 512x16 bytes of ROM. Design the necessary hardware using 512x16 byte RAM and 256x16 byte ROM chips
Consider 2 MBPS I/O device interfaced to 64 bit CPU in a programmed I/O mode. Data transmission between the CPU and I/O in word wise. interrupt overhead is 3 μ sec. What is the performance gain when the device is operating under interrupt I/O over programmed I/O mode? (Please suggest some resource also to study for this topic)
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Consider a computer system has a main memory consisting of 2M 16 bit words. It also has a 8k word cache organized in the block set associative manner, with 4 blocks per set and 32 words per block. What is the number of bits in each of the TAG, SET and word field of main memory address format?
A program is stored in a $\text{16 MB}$ main memory that is attached to a $\text{4 KB}$ direct mapped cache with a block size of $\text{16 bytes}$. The program reads 4 data words $\text{A, B, C and D}$ ... of $400$ memory references $\text{A, B, C and D}$ are located inside the cache. $\text{Which of the above statements is/are TRUE?}$
A system employs 8 stage instruction pipeline in which 1-% instructions results in data dependency, 10% instructions results in control dependency and 5% instructions results in structural dependency. 10% instructions are exposed to data and control dependencies. If the penalty for structural dependency ... for data dependency. What is the average instruction time? a)1.1 cc b)1.4cc 3)1.3cc 4)1.5cc
We are having a five-stage RISC architecture pipeline where the stages are instruction fetch ->decode->execute->memory access->write back, in which we are executing a single instruction ADD R1,R2,R3. As we can see that this instruction doesn’t require a memory access stage then the total number of cycles required to execute this single instruction is 4 cycles or 5 cycles?
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A cache consists of a total of 128 blocks. The main memory contains 2K blocks, each consisting of 32 words. ( I )How many bits are there in each of the TAG, BLOCK and WORD field in case of direct mapping? ( ii )How many bits are there in each of the TAG, SET, and WORD field in case of 4-way set-associative mapping?
Which of the following is false: $(A)$ Interrupts which are initiated by an instruction are software interrupts. $(B)$ When a subroutine is called, the address of the instruction following the CALL instruction is stored in the stack pointer $(C)$ A micro program which is written as 0’s and 1’s is a binary micro program. $(D)$ None of the options.
If a processor has 32-bit virtual address, 28-bit physical address, 2KB pages. How many bits are required for the virtual, physical page number? 17, 21 21, 17 6, 10 None
The addressing mode used in an instruction of the form $ADD\ X\ Y,$ is ___________ (A) Direct (B) Absolute (C) Indirect (D) Indexed
Suppose that a machine A executes a program with an average CPI of 3. Consider another machine B (with the same instruction set and a better compiler) that executes the same program with 10% less instructions and with a CPI of 1.5 at 1.5 GHz. The clock rate of A so that the two machines have the same performance is _______ GHz.
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)
I have a very basic doubt. Let us ignore the fact that we are executing this twice and focus on only executing it once. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S1 S1 S2 S3 S4 NOP S1 S2 S2 S2 S3 S3 S4 S4 NOP S1 S1 NOP S2 NOP S3 NOP S4 ... don't place operations under a NOP, as that is tantamount to both stalling and executing in that particular cycle. If someone could clarify, that'd be of great help.
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4-way set associative LRU cache is used is ________. (Upto 1 decimal places) 100, 104, 108, 104, 107, 108, 105, 102, 108, 103
Consider a CPU that executes at a clock rate of 200 MHz (5 ns per cycle) with a single level of cache. CPIexecution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% arithmetic/logical, 30% load/store, 20% control instruction. Assume the cache miss rate ... a miss penalty of 5 cycles. The number of times cpu with ideal memory is faster when no miss-occurs _______. (Upto 2 decimal places)
Consider a single level cache with an access time of 6 ns, line size of 64 bytes and the hit ratio of 0.8. Main memory uses a block transfer capability that has a first word (8 bytes) access time of 40 ns and 15 ns for each word there after. What is the ... a cache miss? (Assume that the cache waits until the line has been fetched from main memory and re executes for a hit) Anyone please clarify.
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA), Write Back (WB) and their respective time requirements are 9 ns, 3 ns, 7 ns, 9 ns and 2 ns. Assume at each stage the ... the execution is ________ (ns). I getting no of stall 90/4 = 22.5~=23 But in solution they take 22 So which is true ?
Suppose that a processor has access to three levels of memory. Level 1 contain 2000 words and has an access time of 0.02 msec. Level 2 contain 10,000 words and has an access time of 0.2 msec. Level 3 contains 20,000 words and has an access time of 2 msec. Assume that if ... and then accessed. The hit ratio for level 1 is 0.65 and for level 2 is 0.45. The average access time (in μsec) is ________.
Consider a cache consisting of 128 blocks of 16 words each. Main memory has 64 K words and given main memory is 16 bit addressable. The difference between tag memory size of Associative Mapping and Direct Mapping is ________ (bits). Can we take difference in negative here 896
Memory cycle for immediate mode should be 0 is it correct? Consider 1GHz clock frequency processor,uses different operand accessing models shown below: Operand Accessing ModeFrequency(%) Register10 Immediate20 Direct30 Memory Indirect20 Indexed20 Assume that 2 ... /madeeasy-test-series-co-%26-architecture-clock-frequency https://gateoverflow.in/25891/memory-addressing Please check above questions
A full adder is implemented using XOR ,AND,OR gates.the propagation delay of AND and OR gates are half of XOR gates .and propagation delay of XOR gate is 2 ms.a 4 bit ripple carry adder is implemented using 4 full adders . The total propagation delay of 4 bit ripple carry adder will be____? Note:the input given to gates is not restricted to 2.the gates have fan-in more than 2.
A process takes 20 ns on a cache hit and 400 μs on a cache miss to read an instruction. Approximately 20% of the time read request is found in the cache. Then the average access time is ________ μs. (Upto 3 decimal placces)
Consider the cache memory that is 30 times faster than main memory and used 90% of the total time. What is the speedup gain by the cache memory?
consider following set of instructions. I1:ADD R1,R2,R1 I2:LW R2,0(R1) I3:LW R1,4(R1) I4:OR R3,R1,R2 the sum of (RAW ,WAR,WAW) dependencies in given instruction is: please explain why there is not any RAW hazard between I1 and I4
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Given a 32bit processor with 32MB main memory, 32kB 4-set associative on-chip cache and a cache block-size (or line size) of 16 words. What is total no. of tag bit in the memory address format
What will be the answer and how ? plz explain
Can anyone please provide the solution using $pipeline$ $chart?$
Consider a cache memory which is 30 times faster than main memory and it can be used 90% of the time. Speed up gained by the cache memory is ____.
This is a question from GATE 2006, and the given answer says that we will have 4 RAW dependencies. However, I mailed a professor from IISc today, and this is the conversation that followed: Prof: Only I1-I2, I2-I3 and I4-I5 are RAW dependency. For RAW dependency, you need ... need to think it as a new version of R5. Now I am totally confused - what is the actual answer, what should we do in GATE?
Suppose in a system we store data using arrays, we have $2$ arrays A and B. Array A contains $256$ elements of size $4$ bytes each. The first element is stored at physical address $4096$. Another array B contains $512$ elements of size $4$ bytes each, stored from ... answer would be 0, as then 128 blocks of A and 128 blocks of B would be accessed which would fit exactly in our 256 block cache.
In an enhancement of the design of a CPU, the speed of a floating-point unit has been increased by 20% and the speed of a fixed point unit has been increased by 10%. What is the overall speedup achieved if the ratio of the number of floating-point operations to the ... -point operation used to take twice the time taken by the fixed point operation in the original design? 1.155 1.185 1.255 1.285
A RISC processor has 208 registers, 16 register windows. Each window has 4 inputs, 8 local and 4 output registers. The total number of global registers are ?
A computer uses $8$ digit mantissa and $2$ digit exponent. If $a = 0.052$ and $b = 28E + 11$ then $b+a-b$ will result in underflow result in overflow $0$ $5.28 E + 11$