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Welcome to GATE CSE Doubts, where you can ask questions and receive answers from other members of the community.

Recent questions tagged digital-electronics

0 votes
1 answer 12 views
A multiplexer combines four 100-Kps channels using a time slot of 2 bits. a) show the output with for arbitrary inputs b) what is the frame rate? c) what is the frame duration? d) what is the bit rate? e) what is the bit duration?
asked Jul 12 in IIITH-PGEE Cossy 5 points 12 views
0 votes
0 answers 8 views
If some T FFs are connected in series. The 1st FF is supplied by a clock with frequency 1 MHz and the last FF signal out is 31.25 KHz. Find the number of the Flip Flops are used in the circuit.
asked Jun 15 in Digital Logic Emanjse 5 points 8 views
0 votes
0 answers 28 views
What would be the asnwer to this question if FF0 = 10ns FF1 = 20ns FF2 = 30ns AND gate = 10ns
asked Sep 1, 2020 in Digital Logic suvradip das 129 points 28 views
0 votes
1 answer 31 views
What is the difference between parallel counters and serial counters? Is that parallel counter is synchronous counter and serial counter is asynchronous counter?
asked Aug 25, 2020 in Digital Logic Dheeraj Varma 19 points 31 views
1 vote
1 answer 37 views
$Section \space 6.2.2$ is about clocked RS flip flop. My doubt is if we have a NAND based clocked RS flip flop and if inputs $S$ and $R$ are $0$ and $0$ shouldn't this be an invalid state? My thinking is that since it is NAND based RS flip flop which at ... output of 1 and 1 which we know is invalid or forbidden state. So, wouldn't this be applicable if we have a NAND based clocked RS flip flop?
asked Aug 24, 2020 in Digital Logic falgun09 9 points 37 views
0 votes
2 answers 68 views
Please explain briefly – how to approach questions like these. Also, few resources where I can learn the concept required to solve such questions. Answer given is – b.
asked Aug 19, 2020 in Digital Logic Kindaichi 10 points 68 views
1 vote
1 answer 41 views
Why we are using 2421 code when we have 8421 BCD and XS-3 code already? What is the need of introducing the new system format?
asked Aug 19, 2020 in Digital Logic sparshgarg 9 points 41 views
0 votes
2 answers 58 views
How many addition and substraction are required if you perform multiplication of 5 (multiplcand 1 & -30 multiplier) using Booth Algorithm ?
asked Aug 19, 2020 in Digital Logic aryan04 7 points 58 views
0 votes
1 answer 36 views
The gates $G_{1}$ and $G_{2}$ in the figure have the propagation delay of 10 nsec and 20 nsec respectively. If the input $V_{i}$ makes an abrupt change from logic 0 to logic 1 at time t = $t_{0}$ then the output waveform $V_{0}$ is – Answer given is – b. Please explain in detail.
asked Aug 17, 2020 in Digital Logic Kindaichi 10 points 36 views
0 votes
0 answers 87 views
For the given combinational network with three inputs A, B and C, three intermediate outputs P, Q and R, and two final outputs X = P ⋅ Q = ∑(0, 2, 4) and Y = P ⋅ R = ∑(1, 2, 4, 6) as shown below. Find the smallest function P(containing minimum number of min terms that can produce the output x and y) B is the correct answer but how?
asked Jun 10, 2020 in Digital Logic siddharths067 10 points 87 views
0 votes
0 answers 20 views
Options are A).1.7 B).2.4 C).3.5 D).3.3 Please provide the solution also :)
asked Jan 5, 2020 in Digital Logic pass_i0n 5 points 20 views
0 votes
1 answer 81 views
We have a 8-bit ripple carry adder which is implemented by Cascading Full adders. Full adders are also made by the combination of OR, AND and XOR gate. Assume that Sum has 8 ns delay and Carry has 6 ns delay. Find the time taken to find the sum in the worst case.
asked Dec 19, 2019 in Digital Logic shubham02 9 points 81 views
0 votes
0 answers 27 views
Consider the following minterm representation of the function F(x,y,z)=∑(1,2,3,4,5), how many two input NAND gates are required to implement this function, assume that all the inputs and their complements are available.
asked Dec 19, 2019 in Digital Logic shubham02 9 points 27 views
0 votes
0 answers 30 views
Memory & Cache I have a cache which satisfies following conditions; Cache capacity is 8 words, Block size: 2 words, N= 1. How can I calculate the total cache memory size in number of bits? Including the V bits? My cache probably looks something like this, but with 4 sets instead of 2
asked Dec 17, 2019 in CO & Architecture Ccavcav 5 points 30 views
0 votes
0 answers 35 views
Can anybody explain the concept of power button. and explain this question
asked Sep 26, 2019 in Digital Logic Shawn Frost 11 points 35 views
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