Recent questions tagged digital-logic

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How to solve such question.
The number of 1's in 8-bits representation of -127 in 2's complement form is m and that in 1's complement form is n. What is the value of m : n? Options are: 2:1 1:2 3:1 1:3

asked 5 days ago in Digital Logic by `JEET (159 points) | 5 views

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GATEBOOK Floating point 16 bit
Consider the 16 bit floating-point format which has 9 rightmost bits for the mantissa and 6 bits for the excess-31 exponent in the middle and most significant bit stands for sign of the float number. Which of the following represents the difference between the smallest and third ... positive float value in this system? $2^{-39}$ $2^{-40}$ $2^{-38}$ $2^{-37}$

asked 5 days ago in Digital Logic by Mk Utkarsh (111 points) | 19 views

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1 answer

GATEBOOK - IEEE754 Hexadecimal to Decimal
Which of the following real numbers represents IEEE-754 standard single precision floating point value $0x40200000$ to its correct decimal value: 2.5 3.5 4.125 5.125

asked 5 days ago in Digital Logic by Mk Utkarsh (111 points) | 8 views

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Gatebook Floating Point
Consider the 16-bit floating-point format which has 9 rightmost bits for the mantissa and 6 bits for the excess-31 exponent in the middle and most significant bit stands for sign of the float number. Which of the following represents the difference between the largest and eighth largest normalized positive float value in this system? $2^{22}$ $2^{23}$ $2^{24}$ $2^{25}$

asked 5 days ago in Digital Logic by Mk Utkarsh (111 points) | 37 views

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Digital Doubt regarding minimal and irredundant expression

asked Aug 15 in Digital Logic by DukeThunders (208 points) | 12 views

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Vani Question Bank:Digital
A 4 bit parallel binary adder is built using four full adders. If each full adder takes 52ns to produce the sum bit and 20ns to produce carry bit, then the time required for addition of two 4-bit numbers is __________ns.

asked Aug 14 in Digital Logic by Hirak (1.3k points) | 8 views

+1 vote

1 answer

Self doubt : $2's$ complement
Why $2’s$ complement operation generally used for subtraction?

asked Aug 13 in Digital Logic by srestha (247 points) | 15 views

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Self doubt: Digital logic 1
Is it a counter circuit?How to recognize ? If all flip-flop are reset state at first, what is it’s output at Y after $5$ th clock pulse?

asked Aug 11 in Digital Logic by srestha (247 points) | 21 views

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Made Easy Test Series: Digital Logic-IEEE double precision

asked Aug 10 in Digital Logic by srestha (247 points) | 5 views

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Digital logic doubt
K-map can be used upto n variables. What is the value of n ? Is it 5 ?

asked Aug 7 in Digital Logic by user2525 (1.6k points) | 17 views

+3 votes

2 answers

Self doubt: implicants
How many implicant, prime implicant and essential prime implicants are present in the given k-map

asked Jul 28 in Digital Logic by Verma Ashish (305 points) | 45 views

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Gradeup Quiz digital logic
A 1-input, 2-output synchronous sequential circuit behaves as follows: Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk+nk=k). The circuit outputs 00 until one of the following conditions holds. ... is 01. What is the minimum number of states required in the state transition graph of the above circuit? pls explain the question

asked Jul 26 in Digital Logic by aditi19 (134 points) | 8 views

+1 vote

1 answer

Test series Made easy
Minimum no. of NOR gates required to implement ===> (A+B+C)’ ?

asked Jul 23 in Digital Logic by Priyansh Singh (107 points) | 6 views

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1 answer

Made easy digital electronics
Can A number in number system other then decimal be squared using same way as one does with decimal if not how come the first step of solution.

asked Jul 20 in Digital Logic by Ayushgupta (102 points) | 8 views

+1 vote

1 answer

Virtual Gate Test series

asked Jul 16 in Digital Logic by aditi19 (134 points) | 28 views

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Virtual Gate
In the circuit shown in figure, value of input P goes from 0 to 1 and that of Q goes from 1 to 0. Which output forms shown in figure represents the output under a static hazard condition?

asked Jul 15 in Digital Logic by aditi19 (134 points) | 8 views

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2 answers

Digital electronics worksheet from my coaching institution

asked Jul 15 in Digital Logic by Palash yadav (104 points) | 15 views

–1 vote

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Made easy test series digital logic

asked Jul 14 in Digital Logic by Shivani Santoshi (101 points) | 22 views

+1 vote

1 answer

Self Doubt Digital Logic
In a 4-bit carry look ahead adder, the propagation delay of EX-OR gate is 20 ns, AND and OR gates is 10 ns. The sum and carry output of full adder takes 20 ns and 10 ns respectively. The total propagation delay of the above adder in ns is ?

asked Jul 9 in Digital Logic by Sambhrant Maurya (281 points) | 28 views

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VirtualGate Test Series 2018
A microprocessor has an instruction XOR(r1, r2) which performs an Exclusive OR operation of registers r1, r2 and stores the result in r1. After the following instructions are executed XOR(r2, r1) XOR(r1, r2) XOR(r2, r1) Which one of the ... r2 is half sum of r1 and r2 Contents of registers r1 and r2 remain unaltered Contents of registers r1 and r2 are registered

asked Jul 9 in Digital Logic by Sambhrant Maurya (281 points) | 5 views

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1 answer

Self Doubt:Digital Logic
A number has 25 decimal digits. The minimum number of bits required for its representation in binary is?

asked Jul 9 in Digital Logic by Sambhrant Maurya (281 points) | 11 views

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VirtualGate test series 2019
In the circuit shown in figure, value of input P goes from 0 to 1 and that of Q goes from 1 to 0. Which output forms shown in figure represents the output under a static hazard condition?

asked Jul 9 in Digital Logic by Sambhrant Maurya (281 points) | 11 views

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Self doubt: Digital Logic
What are synchronous series carry and parallel carry counters?

asked Jul 9 in Digital Logic by Sambhrant Maurya (281 points) | 5 views

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1 answer

GateForum Test Series: Digital Logic
The number of BCD numbers that can be uniquely represented in 2-4-2-1 code is? _______

asked Jul 8 in Digital Logic by Sambhrant Maurya (281 points) | 11 views

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GateBook Test series: Digital Logic
A sequence detector has to be designed to detect a sequence with at most 3 runs of consecutive zeros of length 3. 001000010001000 This sequence has exactly 2 such runs If we implement a sequential circuit with J-K flip flops then minimum number of flip flops required is ----?

asked Jul 7 in Digital Logic by Sambhrant Maurya (281 points) | 14 views

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1 answer

Gatebook TestSeries: Digital Logic
Block diagram of combinational circuit is shown. The number of distinct combinational circuits (w.r.t to functionality) one can implement is ? $2^{n} \times m$ $2^{2^{n}} \times m$ $2^{m \times 2^{n}}$ $2^{2^{n} \times m }$

asked Jul 7 in Digital Logic by Sambhrant Maurya (281 points) | 10 views

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Made Easy Test Series: Digital Logic

asked Jul 6 in Digital Logic by Sambhrant Maurya (281 points) | 17 views

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Gate question
In this question – https://gateoverflow.in/8219/gate2015-1-20 I’m getting two answers option A & D based on choosing MSB as Q3 or Q0. Now for solving this type of problem, how to know that which one to choose as MSB????

asked Jul 3 in Digital Logic by MRINMOY_HALDER (110 points) | 6 views

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doubt regarding counter
Asynchronous counter is always a full-sequence counter or sometimes in some design It is truncated counter ???? Full-sequence counter = Counter having all 2^n possible states. Truncated counter = Counter having less than 2^n possible states

asked Jul 2 in Digital Logic by MRINMOY_HALDER (110 points) | 2 views

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Decoder using NAND gate
Design a 2-to-4 decoder using NAND gates only with enable input

asked Jul 1 in Digital Logic by aditi19 (134 points) | 6 views