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Recent questions tagged digital-logic

Recent questions tagged digital-logic
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0 answers 40 views
Topic : Digital Logic - Adders
I am very much confused while solving the questions involving adder circuits like Half Adder, Full Adder, Ripple Carry Adder, Carry Look Ahead Adder, etc. I can solve none of the questions, and leave almost all questions involving them. My concept ... me some good source from where I can learn them and practice questions on them. It would be really helpful for me.
Abhrajyoti00 asked in Digital Logic Sep 5, 2021
by Abhrajyoti00
5 points
40 views
0 votes
0 answers 59 views
Introduction to logic circuits and logic design using VHDL, chapter combinational logic design, pg-111.
Noob coder asked in Digital Logic Sep 2, 2021
by Noob coder
5 points
59 views
0 votes
0 answers 39 views
Self Doubt about XOR being linear
Why is xor a linear function as specified on multiple online sources? 01 → 11 is decreasing and 10 → 11 is also decreasing. Shouldn't it be non linear. I want to prove why {XOR, NOT} are not functionally complete.
aryavart asked in Digital Logic Aug 24, 2021
by aryavart
73 points
39 views
0 votes
0 answers 42 views
Sequential Circuits (Digital Logic)
Are Synchronous Circuits easy to implement than Asynchronous Circuits OR the opposite? I have seen varying answers on the internet so this got me confused. Any explanation would help.
Rahul Aryan asked in Digital Logic Aug 20, 2021
by Rahul Aryan
5 points
42 views
0 votes
0 answers 34 views
KSET 2015 COMPUTER SCIENCE AND APPLICATION
Consider a combinational circuit designed using ROM that accepts a 3-bit number and generates an output binary number equal to the square of the input number.What is minimum size of the ROM ? (A)3 × 4 (B)3 × 8 (C)8 × 4 (D)8 × 8
rsiddana asked in Digital Logic Aug 12, 2021
by rsiddana
5 points
34 views
0 votes
0 answers 35 views
Morris Mano, Binary System, Question 1.14
For the weighted codes (a) 3, 3, 2, 1 and (b) 4, 4, 3, - 2 for the decimal digits, determine all possible tables so that the 9’s complement of each decimal digit is obtained by changing l’s to 0’s and 0’s to l’s
Sheldon asked in Digital Logic Aug 12, 2021
by Sheldon
5 points
35 views
0 votes
0 answers 32 views
Digital logic and Computer design by morris mano, Digital design by morris mano and michael d cilleti
ykrishnay asked in Digital Logic Aug 6, 2021
by ykrishnay
103 points
32 views
0 votes
0 answers 38 views
Digital Logic and Computer Design - Combinational Circuits
This_is_Nimishka asked in Digital Logic Jul 10, 2021
by This_is_Nimishka
5 points
38 views
0 votes
0 answers 36 views
#digital-logic
Suppose we are using 4-bit carry lookahead adder modules to built a 64-bit adder with a 2- level carry lookahead with ripple carry between the modules. if the delay of base gate(AND OR NOT) is 2 ns , then the worst case delay of 64 bit adder will be _______ ns?
Abhishek tarpara asked in Digital Logic Jul 5, 2021
by Abhishek tarpara
13 points
36 views
0 votes
0 answers 64 views
#testseries #digitallogic #kmap
Which of the following statements are correct? All prime implicants are minterms but all minterms are not prime implicants(PI). If a literal is deleted from a PI then it is no longer remains an implicant. in the k-map, cube corresponding to a prime implicant may be covered by larger cube. Essential prime implicant are those which are appear in final answer.
Abhishek tarpara asked in Digital Logic Jul 5, 2021
by Abhishek tarpara
13 points
64 views
0 votes
0 answers 39 views
Made Easy Postal course 2018 Number System
Result of subtraction while the following unsigned decimal number by taking the 10's complement of the subtrahend 1753-8640
Ananya Raj asked in Digital Logic Jun 26, 2021
by Ananya Raj
5 points
39 views
0 votes
0 answers 87 views
Applied Gate Practice Test
Consider the following counter. If the initial states of Q0(MSB) and Q1(LSB) are 0. What is the sequence Q0 Q1 given by the following diagram?
ketandalvi asked in Digital Logic Jun 13, 2021
by ketandalvi
5 points
87 views
0 votes
0 answers 52 views
Self Doubt(Digital Logic)
Maximum how many number of functions are possible so that F(x,y,z) = F(x,y’,z) ?
Kartik Goyal asked in Digital Logic Jun 5, 2021
by Kartik Goyal
5 points
52 views
0 votes
0 answers 32 views
Testbook Testseries
For implementing Boolean function F (A, B, C, D) = Σm (0, 1, 2, 4, 6, 9, 12, 14) using 8:1 multiplexer with select lines as B, C and D. Which of the following is correct? I0 and I2 are A̅ I0 and I2 are A I1, I3, and I4 are connected to A̅ I5, I6, and I7 are connected to 0
akabravo97 asked in Digital Logic May 20, 2021
by akabravo97
5 points
32 views
0 votes
0 answers 56 views
Made easy test
Explain me this question.
Enolx.21 asked in Digital Logic Feb 5, 2021
by Enolx.21
53 points
56 views
0 votes
1 answer 66 views
Made Easy Workbook
How can we minimize this function? Ans(d)
grv_d asked in Digital Logic Feb 2, 2021
by grv_d
9 points
66 views
1 vote
0 answers 74 views
Self Doubt: Digital logic design
This question is from GATE 2019- Instrumentation branch (Digital logic) Can anyone solve this and can explain what is meant by steady state? Ans: 4
phaneendrababu asked in Digital Logic Jan 23, 2021
by phaneendrababu
11 points
74 views
0 votes
0 answers 132 views
Made Easy Testseries Digital Q4
A flipflop has 3 ns delay from the time the clock edge occurs to the time the output is complemented. What is the maximum frequency at which mod-1024 counter can operate reliably? 33 MHz 40 MHz 33.3 MHz 10 MHz
Shivateja MST asked in Digital Logic Jan 5, 2021
by Shivateja MST
45 points
132 views
0 votes
0 answers 30 views
Unacademy test series Digital Q2
Odd function B. Even Function C. Identity function D. Both B and C
Shivateja MST asked in Digital Logic Dec 19, 2020
by Shivateja MST
45 points
30 views
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