Recent questions tagged digital-logic - GATE CSE Doubts

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TestBook Test
In an SR latch by cross-coupling two NOR gates if S = 1 and R = 0, then, it’ll result in ___? Can anyone please explain the reason?

asked Jun 22 in Digital Logic by Jean (9 points) | 17 views

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MADE EASY TS
I there are 13 flip-flops used is PISO shift register circuit, then maximum number of clock cycles required to get the serial output is _____ ?

asked Jun 9 in Digital Logic by ummokkate (64 points) | 9 views

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MADE EASY TS
The decimal value of the 2’s complement binary number 11101111110.0010 is ________? I got -130.125, but answer is something else.

asked Jun 9 in Digital Logic by ummokkate (64 points) | 9 views

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the gatebook ts
A certain J-K FF has a propagation delay of 12ns. The largest MOD of the counter such that, the counter can be designed from these FFs which will operate up to 10 MHz?

asked Jun 8 in Digital Logic by ummokkate (64 points) | 20 views

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MADE EASY TS
Here my doubt is that when we get the equation of y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3, given I0, I3 are S1 and I1, I2 are S0 so when we will substitute them, will be substitute y = S1’S0’S1 + S1’S0S0 + S1S0’IS0+ S1S0S1 or will we substitute y = S1’S0’S1’ + S1’S0S0 + S1S0’S0’+ S1S0S1 according to the value of select lines. I’m a bit confused.

asked Jun 8 in Digital Logic by ummokkate (64 points) | 12 views

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MADE EASY TS
A function f(x,y,z) = x XNOR y XNOR z = 1, then which of the following is always true? x + yz =1 x not equal to (y XOR z) x.y.z =1 x = y XNOR z I’m getting both option b and option d.

asked Jun 8 in Digital Logic by ummokkate (64 points) | 22 views

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THE GATEBOOK TS
Consider the boolean function that has the don't care states: and . How many prime implicants (P) and essential prime implicants (EP) are there for F? (A). Five (P) and Three (EP) (B). Four (P) and Three (EP) (C). Five (P) and Two (EP) (D). Six ... Three (EP) I'm getting option B, but answer given is option A. Reason given is don't cares will also make 1 PI, can anyone confirm it.

asked Jun 7 in Digital Logic by ummokkate (64 points) | 10 views

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Self doubt on GB: Digital Logic
When two 8-bit numbers and in 2's complement representation (with and as the least significant bits) are subtracted(i.e. A-B) by first negating the subtrahend and then adding it to the minuend using a ripple-carry adder, the sum bits obtained are and the carry ... 1 (B). is 1 (C). is 1 (D). is 1 How this question will differ from previous GATE question? Plz verify

asked Jun 1 in Digital Logic by srestha (749 points) | 18 views

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How we got exponent as $2^{127-64}$?
Information: Consider a 16-bit register of the following format is used to store a floating point number. Mantissa (M) is denoted as normalized signed magnitude fraction, Exponent (E) is expressed in excess-64 form. Base of the system is ... ? Please explain it as you are explaining to naive person. I am missing something very obvious! Waiting for explanation!

asked Apr 24 in Digital Logic by ubibhatt (6 points) | 7 views

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GATE1989-1-vi
It would be helpful if you provide me the solution. i'm not able to understand the solution which is given in go site. please provide me detailed explanation GATE1989-1-vi Consider an excess - 50 representation for floating point ... digit exponent in normalised form. The minimum and maximum positive numbers that can be represented are __________ and _____________ respectively.

asked Apr 20 in Digital Logic by varunraj (9 points) | 7 views

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GATE1992-02-ii
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: All digital circuits can be realized using only A.Ex-OR gates B.Multiplexers C.Half adders D.OR gates I have a doubt in question ... complete or partially functionally complete? multiplexer and Half adders are partially functionally complete.WHAT IS THE ACTUAL ANSWER??????

asked Apr 19 in Digital Logic by varunraj (9 points) | 4 views

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GATE2006-8 digital logic
please explain me the solution and how to draw timing diagrams for this kind of questions?

asked Apr 19 in Digital Logic by varunraj (9 points) | 4 views

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GATE2016-1-8 Video Solution
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.

asked Apr 19 in Digital Logic by admin (3.6k points) | 6 views

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GATE2015-2-48 Video Solution
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is ... binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.

asked Apr 19 in Digital Logic by admin (3.6k points) | 10 views

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GATE2015-2-7 Video Solution
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is _______.

asked Apr 19 in Digital Logic by admin (3.6k points) | 3 views

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GATE2016-1-33 Video Solution
Consider a carry look ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2004-62 Video Solution
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time ... the carry network has been implemented using two-level AND-OR logic. 4 time units 6 time units 10 time units 12 time units

asked Apr 19 in Digital Logic by admin (3.6k points) | 3 views

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GATE2007-34 Video Solution
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n-1}$ line to $1$line $2^{n-2}$ line to $1$line

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2006-38 Video Solution
Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $ i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle $ ... $ wx\overline{y} \overline{z}, xz, w\overline{x}yz$ $ wx\overline{y}, wyz, wxz, \overline{w}xz, x\overline{y}z, xyz$

asked Apr 19 in Digital Logic by admin (3.6k points) | 2 views

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GATE2010-32 Video Solution
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$ $10$, $11$, $01$, $00$ $10$, $00$, $01$, $11$ $11$, $10$, $00$, $01$

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2017-2-12 Video Solution
Given the following binary number in $32$-bit (single precision) $IEEE-754$ format : $\large 00111110011011010000000000000000$ The decimal value closest to this floating-point number is : $1.45*10^1$ $1.45*10^{-1}$ $2.27*10^{-1}$ $2.27*10^1$

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2007-8, ISRO2011-31 Video Solution
How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates? $7$ $8$ $9$ $10$

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2010-7 Video Solution
The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1M \times$ $\text{1-bit}$ DRAM chips. Each DRAM chip has 1K rows of cells with $1K$ cells in each row. The time taken for a single refresh operation is $100$ ... the memory unit is $100$ nanoseconds $100\times 2^{10}$ nanoseconds $100\times 2^{20}$ nanoseconds $3200\times 2^{20}$ nanoseconds

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2019-50 Video Solution
What is the minimum number of $2$-input NOR gates required to implement a $4$ -variable function expressed in sum-of-minterms form as $f=\Sigma(0,2,5,7, 8, 10, 13, 15)?$ Assume that all the inputs and their complements are available. Answer: _______

asked Apr 19 in Digital Logic by admin (3.6k points) | 13 views

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GATE2007-IT-7 Video Solution
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation? $11, 00$ $01, 10$ $10, 01$ $00, 11$

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2007-36 Video Solution
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ ... through the following sequence: $0, 3, 4$ $0, 3, 4, 5$ $0, 1, 2, 3, 4$ $0, 1, 2, 3, 4, 5$

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE1995-2.12, ISRO2015-9 Video Solution
The number of $1$'s in the binary representation of $(3*4096 + 15*256 + 5*16 + 3)$ are: $8$ $9$ $10$ $12$

asked Apr 19 in Digital Logic by admin (3.6k points) | 2 views

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GATE2006-39 Video Solution
We consider the addition of two $2's$ complement numbers $ b_{n-1}b_{n-2}\dots b_{0}$ and $a_{n-1}a_{n-2}\dots a_{0}$. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by $ c_{n-1}c_{n-2}\dots c_{0}$ and the carry-out ... $ c_{out}\oplus c_{n-1}$ $ a_{n-1}\oplus b_{n-1}\oplus c_{n-1}$

asked Apr 19 in Digital Logic by admin (3.6k points) | 2 views

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GATE2001-2.8 Video Solution
Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$ Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?

asked Apr 19 in Digital Logic by admin (3.6k points) | 2 views

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GATE1996-1.25 Video Solution
Consider the following floating-point number representation.$\begin{array}{c|c} \begin{array}{cc}31\;\;\hspace{15pt}&\hspace{15pt}24\end{array} & \begin{array}{cc}23\hspace{15pt}&\hspace{15pt}0\end{array} \\\hline \text{Exponent}&\text{Mantissa}\\ \hline \end{array}$The ... to $1$ $0.5$ to $1$ $2^{-23}$ to $0.5$ $0.5$ to $\left(1-2^{-23}\right)$

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2003-43 Video Solution
The following is a scheme for floating point number representation using 16 bits. Bit Position 15 14 .... 9 8 ...... 0 s e m Sign Exponent Mantissa Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. ... between two successive real numbers representable in this system? $2^{-40}$ $2^{-9}$ $2^{22}$ $2^{31}$

asked Apr 19 in Digital Logic by admin (3.6k points) | 2 views

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GATE2006-8 Video Solution
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

asked Apr 19 in Digital Logic by admin (3.6k points) | 5 views

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GATE2004-18, ISRO2007-31 Video Solution
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in $Q = 0, Q' = 1$ $Q = 1, Q' = 0$ $Q = 1, Q' = 1$ Indeterminate states

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2016-2-07 Video Solution
Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value of $A$ is one, the decimal value of $B$ that leads to the longest latency for the sum to stabilize is ___________

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2006-40 Video Solution
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $ (n+1)(modulo 16)$ ... $ g_{3}(h_{3}h_{2}h_{1}h_{0})=\sum (0,1,6,7,10,11,12,13) $

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2014-2-7 Video Solution
Let $k=2^n$. A circuit is built by giving the output of an $n$-bit binary counter as input to an $n\text{-to-}2^n$ bit decoder. This circuit is equivalent to a $k$-bit binary up counter. $k$-bit binary down counter. $k$--bit ring counter. $k$-bit Johnson counter.

asked Apr 19 in Digital Logic by admin (3.6k points) | 2 views

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GATE2005-62 Video Solution
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let $A_{i}$ represents the logic level on the line a in the i-th clock period. Let $A'$ represent the compliment of $A$. The correct output sequence on $Y$ over the clock periods $1$ ... $A_{1} A_{2} A_{2}' A_{3} A_{4}$ $A_{1} A_{2}' A_{3} A_{4} A_{5}'$

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE1996-1.21 Video Solution
A ROM is used to store the table for multiplication of two $8$-bit unsigned integers. The size of ROM required is $256 \times 16$ $64 K \times 8$ $4 K \times 16$ $64 K \times 16$

asked Apr 19 in Digital Logic by admin (3.6k points) | 9 views

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GATE2005-IT-43 Video Solution
Which of the following input sequences will always generate a $1$ at the output $z$ ...

asked Apr 19 in Digital Logic by admin (3.6k points) | 1 view

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GATE2019-22 Video Solution
Two numbers are chosen independently and uniformly at random from the set $\{1,2,\ldots,13\}.$ The probability (rounded off to 3 decimal places) that their $4-bit$ (unsigned) binary representations have the same most significant bit is _______________.

asked Apr 19 in Digital Logic by admin (3.6k points) | 4 views

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