Recent questions tagged digital-logic - GATE CSE Doubts

0 votes

0 answers

Self doubt:MADE EASY: COUNTERS
Is there any other states in the output other than $000$ and $111?$ All the flips flops are given only $toggle$ input right? So shouldnt it be $mod2$ counter?

asked 1 day ago in Digital Logic by Debapaul (652 points) | 12 views

0 votes

1 answer

Made easy test series, DLD-Counters
How is it mod-5 counter?please explain

asked 2 days ago in Digital Logic by Dheeraj Varma (21 points) | 44 views

0 votes

0 answers

testbook advance 3 counter
above circuit is: MOD 7 UP COUNTER MOD 13 UP COUNTER MOD 1 UP COUNTER MOD 1 DOWN COUNTER

asked 2 days ago in Digital Logic by abhinav649 (65 points) | 9 views

0 votes

1 answer

Digital logic Ace test series

asked 4 days ago in Digital Logic by Chirag Shilwant (167 points) | 24 views

0 votes

0 answers

ace test series mock test 7
8.

asked 4 days ago in Digital Logic by Rahul Burman (21 points) | 17 views

0 votes

0 answers

applied gate: mock dld
The total number of minimal POS expressions present for a K-map having total of 8 minterms out of which 5 are covered by Essential prime implicants while remaining minterms are covered by 3 non essential prime implicant.

asked 4 days ago in Digital Logic by abhinav649 (65 points) | 7 views

0 votes

0 answers

asked 5 days ago in Digital Logic by Chirag Shilwant (167 points) | 14 views

0 votes

0 answers

ME Test Propagation Delay

asked Jan 14 in Digital Logic by kashyap02 (14 points) | 15 views

0 votes

0 answers

GATE GURU: WORK BOOK
Binary to Gray Binary to excess 3 Gray to Binary BCD to binary

asked Jan 14 in Digital Logic by Debapaul (652 points) | 16 views

0 votes

1 answer

MADE EASY ADVANCE LEVEL DIGITAL
$\sum m(2,3,6,7)$ $\sum m(0,1,2,3)$ $\sum m(0,1,4,5)$ $\sum m(4,5,6,7)$

asked Jan 13 in Digital Logic by Debapaul (652 points) | 17 views

0 votes

0 answers

Made Easy test series multiple subject digital adder

asked Jan 8 in Digital Logic by Ram Swaroop (171 points) | 12 views

0 votes

0 answers

TestSeries Doubt
Options are A).1.7 B).2.4 C).3.5 D).3.3 Please provide the solution also :)

asked Jan 5 in Digital Logic by pass_i0n (14 points) | 11 views

0 votes

1 answer

Self Doubt: Digital
$Proof$ $y+\overline{x}$ $\overline{y}= y+ \overline{x}$ Don’t proof it using table method, I want to know how u solved the $LHS$ to get the $RHS?$

asked Jan 2 in Digital Logic by Debapaul (652 points) | 25 views

0 votes

0 answers

Combinational Circuits
What is the minimum size of the ROM required to implement the following set of Boolean equations? F1(w,x,y,z) = $\sum$ m(0, 1, 2, 5, 7, 12, 13, 15) F2(w,x,y,z) = $\sum$ m(0, 5, 6, 9, 13, 15) F3(w,x,y,z) = $\sum$ m(6, 7, 9, 12, 14,15) (a) 16 $\times$ 4 (b) 16 $\times$ 3 (c)16 $\times$ 8 (d) 16 $\times$ 12

asked Dec 30, 2019 in Digital Logic by haralk10 (54 points) | 11 views

0 votes

1 answer

MOCK DEMO madeeasy Q18
Both f and g are functionally complete. only f is functionally complete. only g is functionally complete neither f nor g is functionally complete. please describe the procedure

asked Dec 30, 2019 in Digital Logic by ssap09 (42 points) | 41 views

0 votes

0 answers

Ravindrababu test series
a).11 b)10 c) 9 d)12 & Please Explain the method to solve also:)

asked Dec 19, 2019 in Digital Logic by pass_i0n (14 points) | 30 views

0 votes

0 answers

Made Easy Digital Logic
The minimum no. of NAND gates needed to implement the function $Y=(B+C)(A'+D')$ is? Is there a general procedure for this? I get it wrong many times. I converted it to SOP to get Y = BA’ + BD’ + CA’ + CD’ which cannot be further minimized, giving 5 NAND gates. But the ans is 4 :(

asked Dec 15, 2019 in Digital Logic by Sambhrant Maurya (343 points) | 12 views

0 votes

0 answers

GATE 2018 EE
The circuit below shows an up/down counter working with a decoder and a flipflop. Preset and Clear of the flip-flop are asynchronous active-low inputs. Assuming that the initial value of counter output (Q2Q1Q0) as zero, the counter output in decimal for 12 clock cycles are (A) 0, 1, 2, 3, 4, 4, 3, 2, 1, 1, 2, 3, ... 3, 4, 5, 5, 4, 3, 2, 1, 0, 1 (D) 0, 1, 2, 3, 4, 5, 4, 3, 2, 1, 0, 1, 2

asked Dec 13, 2019 in Digital Logic by Sambhrant Maurya (343 points) | 4 views

0 votes

0 answers

GATE 2003 IN
The square wave $C_{1}$ shown in the figure is given to the clock input of a 4-bit binary up/down counter whose UP/ DN input is fed with the pulse train $P_{U}$. The counter is a negative edge triggered one. The counter starts with 0000 and will reach 0000 again at the (A) 15th clock pulse (B) 16th clock pulse (C) 44th clock pulse (D) 48th clock pulse

asked Dec 13, 2019 in Digital Logic by Sambhrant Maurya (343 points) | 3 views

0 votes

0 answers

Self Doubt: K maps
$f_{1}(A,B,C,D) = \sum(0,1,8,9) + d(2,10,5)$ $f_{2}(A,B,C,D) = \sum(0,2,9,14) + d(1,8,15)$ Then what is f1 + f2 and f1 . f2 respectively? How to deal with the don’t cares?

asked Dec 12, 2019 in Digital Logic by Sambhrant Maurya (343 points) | 10 views

0 votes

1 answer

asked Dec 12, 2019 in Digital Logic by gull kaur (10 points) | 10 views

0 votes

0 answers

Made Easy: Digital Logic
In the logic circuit above, input at line $I_{13}$ in 16 X 1 MUX corresponds to output at line $I'_{n}$ of 1 X 16 DeMUX. What is the value of n?

asked Dec 11, 2019 in Digital Logic by Sambhrant Maurya (343 points) | 17 views

0 votes

0 answers

Self doubt in digital logic
https://gateoverflow.in/233283/pi-and-epi-in-case-of-dont-care?show=328136#c328136 In that question answer explains that all x's(don't care terms) can be combined to form a prime implicant. But my doubt is that even if any ... group occurs functions value may not be true. Because by definition implicant is that whose truthness implies truthness of function. Thanks.

asked Dec 7, 2019 in Digital Logic by Vimal Patel (886 points) | 4 views

0 votes

0 answers

Made easy test series: sequential circuit
Answer is given as 33.33 MHz. But my doubt is that they have considered only NAND gates and not flip flops which will give mod 4 counter, due to which answer should be 33.33 / 4 = 8.33 MHz Am i right or wrong?

asked Dec 2, 2019 in Digital Logic by vishal burnwal (125 points) | 6 views

0 votes

0 answers

Made easy practice questions book

asked Dec 2, 2019 in Digital Logic by Jyoti Kumari97 (24 points) | 14 views

0 votes

0 answers

Made-easy-booklet

asked Dec 2, 2019 in Digital Logic by Jyoti Kumari97 (24 points) | 6 views

0 votes

0 answers

Made easy practice questions book 2019

asked Dec 2, 2019 in Digital Logic by Jyoti Kumari97 (24 points) | 6 views

0 votes

1 answer

Self Doubt - MUX
$1)$ If we want to implement $n$ variable function with $2^{n}\times 1$ MUX, is it possible? $2)$ If we want to implement $n$ variable function with $2^{n}\times 1$ MUX and with NOT gate, is it possible? Someone plz xplain which one possible and which one not possible, and why??

asked Nov 29, 2019 in Digital Logic by srestha (641 points) | 21 views

0 votes

0 answers

Self Doubt-GATE question
Please check this ques https://gateoverflow.in/1057/gate2004-62 How it could be done in 6 unit time? I think EXOR gate itself need 4 NAND gate. So, And 3 NAND gate is required. Isnot it? Now, 3 AND gate and 2 OR gate required to complete the circuit. Isnot it?

asked Nov 27, 2019 in Digital Logic by srestha (641 points) | 18 views

0 votes

1 answer

ACE-NAND GATEs
To design $16$ input NAND gate, the number of $2$ input NAND gate required is ______________ Ans given 29,with a formula 2n-3, but why? I think last level required 8 NAND gate 2nd level required 4 NAND gates Similarly 3rd level 2 and 4th level 1 NAND gates, so, total 15 NAND gates. Where Am I going wrong?

asked Nov 26, 2019 in Digital Logic by srestha (641 points) | 18 views

0 votes

1 answer

Digital GATE1993-6.2 Question Doubt.
Source – https://gateoverflow.in/17235/gate1993-6-2 Can someone please explain this question. I am not getting the explanation provided. Thanks!

asked Nov 23, 2019 in Digital Logic by iarnav (76 points) | 24 views

0 votes

1 answer

Digitallogic question
How many no of ternary functions are possible with 2 boolean variables? Is this correct logically? I mean with 2 boolean variables we can have functions of just 2 variables at maximum right? Anyone please clarify.

asked Nov 22, 2019 in Digital Logic by Shivateja MST (100 points) | 37 views

0 votes

1 answer

Self doubt : In boolean expression simplification
suppose we have something like this: f1(p,q,r) = minterms(1,3,7) f2(p,q,r) = minterms(0,3,6) F = minterms( f1’.f2’ ) = minterms( (1,3,7)’.(0,3,6)’ ) How we simplify this F function directly?

asked Nov 22, 2019 in Digital Logic by shaktisingh (90 points) | 21 views

0 votes

0 answers

self doubt: Multiplexer are functionally complete or partially functionally complete

asked Nov 21, 2019 in Digital Logic by shaktisingh (90 points) | 22 views

+1 vote

0 answers

Self Doubt: r's complement
Is this ans correct? https://gateoverflow.in/235417/ace-test-series-digital-logic-number-system We know that 7's complement of a number is $7777 .- x$ , where x can be any number. And for 8's complement we need to add $1$ with it. Means for ... add 1, Isnot it? Then how in this question ,we are subtracting directly from 8888, which is an even number? Plz someone tell me.

asked Nov 21, 2019 in Digital Logic by srestha (641 points) | 14 views

+1 vote

2 answers

Success gateway test series
$f_{1}(A,B,C,D)=\Sigma m(0,1,8,9)+\Sigma d(2,10,15)$ $f_{2}(A,B,C,D)=\Sigma m(0,2,9,14)+\Sigma d(1,8,15)$ What is $f_{1}+f_{2}$ and $f_{1}.f_{2}$

asked Nov 20, 2019 in Digital Logic by aditi19 (55 points) | 63 views

0 votes

0 answers

UEMK GATE MOCK :DIGITAL
What will be the ans , and how to approach?

asked Nov 16, 2019 in Digital Logic by Debapaul (652 points) | 15 views

0 votes

0 answers

Self doubts dld
$F(a,b,c)=F(\bar{a},\bar{b},\bar{c})$ no function possible

asked Nov 13, 2019 in Digital Logic by amit166 (138 points) | 12 views

0 votes

0 answers

#DLD How to find delay in Carry look ahead adder?
Ques 1) Exclusive−OR gate has a propagation delay of 10 ns and that the AND or OR gates have a propagation delay of 5 ns.What is the total propagation delay time in the four-bit adder.Assume FAN−IN=2 1) ripple adder 2) ... -ripple-carry Ques 2) https://gateoverflow.in/80674/can-anybody-explain-carry-look-ahead-delay-delay-and-and-and Thank you!

asked Nov 9, 2019 in Digital Logic by iarnav (76 points) | 8 views

+2 votes

1 answer

GATE GURU 2020: DLD
Minimum number of NOR gates required to implement (A+B+C)’ is_______________ . 4 3 2 5 How to approach these types of question, I always do mistakes in these

asked Nov 4, 2019 in Digital Logic by Debapaul (652 points) | 51 views

Page:

1
2
3
next »

3,138 questions

1,550 answers

9,401 comments

89,835 users