Recent questions tagged digital-logic - GATE CSE Doubts

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Madeeasypostal ACE
"GATE CSE 2000 | Question: 1.6 - GATE Overflow" https://gateoverflow.in/629/gate-cse-2000-question-1-6 In question above we understood that positive number and unsigned is represented same as in 2's complement. here in question below the hex number is ... be same as number given is positive(bcoz msb is not 7). Determine 8's compliment of an octal number 2670? Right??

asked 5 days ago in Digital Logic by BhaktiDhorajiya (5 points) | 8 views

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ACE TEST SERIES
WHICH OF THE FOLLOWING INDICATES 8`s COMPLEMENT OF $[70700]_8$ IN SIX DIGIT? $[707100]_8$ $[007100]_8$ $[707078]_8$ $[007078]_8$

asked May 3 in Digital Logic by abhishek.maurya (5 points) | 10 views

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Principle of Duality (Digital Logic)
What will be the dual of the following expression? A + B’.[C’+D(E+F’)]

asked May 2 in Digital Logic by gargi24 (5 points) | 20 views

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2's complement
how did the range of 2’s complement is -2^(n-1) to (2^(n-1) -1)? particularly for the lower limit?

asked May 2 in Digital Logic by JAINchiNMay (5 points) | 6 views

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Made easy test
Explain me this question with boolean function form.(not k map)

asked Feb 5 in Digital Logic by Enolx.21 (49 points) | 41 views

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Made easy test
Explain me this question.

asked Feb 5 in Digital Logic by Enolx.21 (49 points) | 21 views

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1 answer

Made Easy Workbook
How can we minimize this function? Ans(d)

asked Feb 2 in Digital Logic by grv_d (9 points) | 40 views

+1 vote

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Self Doubt: Digital logic design
This question is from GATE 2019- Instrumentation branch (Digital logic) Can anyone solve this and can explain what is meant by steady state? Ans: 4

asked Jan 23 in Digital Logic by phaneendrababu (11 points) | 48 views

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Made Easy Testseries Digital Q4
A flipflop has 3 ns delay from the time the clock edge occurs to the time the output is complemented. What is the maximum frequency at which mod-1024 counter can operate reliably? 33 MHz 40 MHz 33.3 MHz 10 MHz

asked Jan 5 in Digital Logic by Shivateja MST (45 points) | 50 views

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Applied Ai Test Series
2’s complement representation for (12121) base 3 ? 10010111 base 2 01011011 base 2 01011111 base 2 01011010 base 2

asked Dec 21, 2020 in Digital Logic by GATE2021_ayush (5 points) | 20 views

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Unacademy test series Digital Q2
Odd function B. Even Function C. Identity function D. Both B and C

asked Dec 19, 2020 in Digital Logic by Shivateja MST (45 points) | 19 views

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Unacademy Digital Quesn 1
A 1-bit full adder takes 20ns to generate a carryout bit and takes 40ns to generate a sum bit. The maximum rate of addition per second when four 1-bit full adder are cascaded is _______ x 10^7. Anyone please clarify.

asked Dec 18, 2020 in Digital Logic by Shivateja MST (45 points) | 56 views

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Self doubt - digital logic
K-map 0 1 0 0 0 1 X 0 0 X X 0 0 0 0 0 X= don’t care Derive the minimum Sum-of-Product form for this.

asked Dec 17, 2020 in Digital Logic by Abhishek pratap Sing (5 points) | 23 views

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login gate multiple value logic

asked Dec 17, 2020 in IS&Software Engineering by Behrooz14255 (5 points) | 21 views

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4-bit synchronous up-down counter designed using a T-flip flow.

asked Dec 16, 2020 in Digital Logic by junpyo (5 points) | 14 views

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Made easy Digital Logic Q1
Anyone please clarify. I feel answer to be 16 ms.

asked Dec 15, 2020 in Digital Logic by Shivateja MST (45 points) | 49 views

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Question taken from book morris mano 3rd edition chapter 3 question number 26

asked Dec 14, 2020 in Digital Logic by fahad137 (5 points) | 15 views

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#self-doubt #logic-design
IN excess 3 code -The binary sum of a code and its 9′s complement is equal to 9. can someone explains meaning of this statement with example.

asked Dec 6, 2020 in Digital Logic by 404 found (37 points) | 28 views

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Made Easy test series
How to know through representation which one is LSB and which one is MSB

asked Dec 3, 2020 in Digital Logic by vimal12 (5 points) | 22 views

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Made Easy TextBook Assignments Counters #self doubt

asked Dec 1, 2020 in Digital Logic by ayusha5312 (21 points) | 25 views

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Made Easy Text Book Counters 2018 Delay of ripple counter and synchronous counter

asked Nov 30, 2020 in Digital Logic by ayusha5312 (21 points) | 14 views

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Made Easy Text Book Counters 2018 Delay of ripple counter and synchronous counter

asked Nov 30, 2020 in Digital Logic by ayusha5312 (21 points) | 18 views

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Made Easy TextBook Counters Gate CS .#Self Doubt
Please provide detailed solution.

asked Nov 29, 2020 in Digital Logic by ayusha5312 (21 points) | 38 views

+3 votes

1 answer

Gateoverflow test series question.
Assume that the propagation delay in each gate in a 16-bit ripple carry adder (made of AND, OR, and NOT gates only with up to 3 inputs) is 1 ns. Time taken in nanoseconds to perform a 16-bit addition is _______. Given answer is 33 nanoseconds. How to solve this question?

asked Nov 29, 2020 in Digital Logic by CSHuB (33 points) | 94 views

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NIC STA 2020 SET A 54
Q. How many AND, OR and XOR gate are required for implementation of full adder? A) 1,2,2 B) 2,2,1 C) 3,2,2 D) 3,0,1 I think none of the option match Plz check

asked Nov 27, 2020 in Digital Logic by Hradesh patel (9 points) | 19 views

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NiC STA 2020 set A 111
Q. Encoder are made by three.......gates. A) AND B) OR C) NAND D) XOR I think question framing wrong Plz check

asked Nov 27, 2020 in Digital Logic by Hradesh patel (9 points) | 20 views

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1 answer

Made Easy Sequential Circuits 2018 #self doubt
Please provide the detailed solution!

asked Nov 26, 2020 in Digital Logic by ayusha5312 (21 points) | 24 views

+1 vote

1 answer

Made Easy Text Book Sequential Circuit #2018 #JK Flip Flops

asked Nov 25, 2020 in Digital Logic by ayusha5312 (21 points) | 20 views

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1 answer

MadeEasy text book Digital logic Combinational circuits 2018

asked Nov 23, 2020 in Digital Logic by ayusha5312 (21 points) | 29 views

+1 vote

1 answer

MadeEasy textbook Digital logic combinational circuits

asked Nov 23, 2020 in Digital Logic by ayusha5312 (21 points) | 25 views

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Sequential Circuit
Draw the sequential circuit for serial adder using shift registers, full adder and D-FF. Explain its operation with state equations and state table .

asked Nov 19, 2020 in Digital Logic by Asad5059 (5 points) | 18 views

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Will Download B.S. Grewals in Higher Mathematics bring antivirus？

asked Nov 18, 2020 in Digital Logic by Ellalucky (5 points) | 17 views

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#made-easy-test-series
Number of literals present in the boolean expression given below: cd+b(comp.)d(comp.)+ac+a(comp)bd ans in solution is 9 did we have to count literal in each and every term uniquely or we have to count only unique literals (then ans will be 4).

asked Nov 16, 2020 in Digital Logic by 404 found (37 points) | 22 views

+1 vote

1 answer

made easy grand test question

asked Nov 15, 2020 in Digital Logic by ijnuhb (747 points) | 59 views

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2 answers

Madeeasy Testseries question
III only IV only I, II, III only I, II, IV only Clearly IV is wrong and III is right. I feel I and II need not be true. Anyone please clarify.

asked Oct 27, 2020 in Digital Logic by Shivateja MST (45 points) | 78 views

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1 answer

internet social media

asked Oct 15, 2020 in Digital Logic by Love Barot (7 points) | 54 views

+1 vote

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Made easy Test Series, Digital Logic, Counters
Hello, I have a doubt here. It is given that we have a cascaded counter with : Counter C1 as Mod 2 counter and C2 as Mod 3 counter. Therefore I can assume that C1 uses 1 flip-flop and C2 uses 2 flipflops. Now assuming the ... the solution (it is given 1000 KHz). Can anyone explain me the given solution? How they have arrived at the equation? Thanks!

asked Sep 21, 2020 in Digital Logic by sankalpmittal (41 points) | 53 views

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Made Easy Test Series, Digital Logic , Combinational Circuits

asked Sep 21, 2020 in Digital Logic by sankalpmittal (41 points) | 73 views

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Made Easy Topic Test - 2021
Consider the Function f(w,x,y,z) = $\sum m$ (0,4,5,10,14,15 ) + d(7,13) . The number of essential prime implicants are ____ . PS: My answer came out to be 2.

asked Sep 3, 2020 in Digital Logic by dipanjan (9 points) | 44 views

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Made Easy Topic Test - 2021
Determine the Hazard Free SOP Expression for f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD’ + A’C’D + AB’C f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD’ + AB’C’ + A’B’D + A’C’D f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD’ + AB’C

asked Sep 3, 2020 in Digital Logic by dipanjan (9 points) | 29 views

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