Recent questions tagged digital-logic - GATE CSE Doubts

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Self Doubt: K maps
$f_{1}(A,B,C,D) = \sum(0,1,8,9) + d(2,10,5)$ $f_{2}(A,B,C,D) = \sum(0,2,9,14) + d(1,8,15)$ Then what is f1 + f2 and f1 . f2 respectively? How to deal with the don’t cares?

asked 4 minutes ago in Digital Logic by Sambhrant Maurya (290 points) | 1 view

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asked 5 hours ago in Digital Logic by gull kaur (10 points) | 4 views

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Made Easy: Digital Logic
In the logic circuit above, input at line $I_{13}$ in 16 X 1 MUX corresponds to output at line $I'_{n}$ of 1 X 16 DeMUX. What is the value of n?

asked 1 day ago in Digital Logic by Sambhrant Maurya (290 points) | 12 views

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Self doubt in digital logic
https://gateoverflow.in/233283/pi-and-epi-in-case-of-dont-care?show=328136#c328136 In that question answer explains that all x's(don't care terms) can be combined to form a prime implicant. But my doubt is that even if any ... group occurs functions value may not be true. Because by definition implicant is that whose truthness implies truthness of function. Thanks.

asked 5 days ago in Digital Logic by Vimal Patel (387 points) | 3 views

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Made easy test series: sequential circuit
Answer is given as 33.33 MHz. But my doubt is that they have considered only NAND gates and not flip flops which will give mod 4 counter, due to which answer should be 33.33 / 4 = 8.33 MHz Am i right or wrong?

asked Dec 2 in Digital Logic by vishal burnwal (57 points) | 5 views

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Made easy practice questions book

asked Dec 2 in Digital Logic by Jyoti Kumari97 (18 points) | 14 views

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Made-easy-booklet

asked Dec 2 in Digital Logic by Jyoti Kumari97 (18 points) | 6 views

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Made easy practice questions book 2019

asked Dec 2 in Digital Logic by Jyoti Kumari97 (18 points) | 6 views

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Self Doubt - MUX
$1)$ If we want to implement $n$ variable function with $2^{n}\times 1$ MUX, is it possible? $2)$ If we want to implement $n$ variable function with $2^{n}\times 1$ MUX and with NOT gate, is it possible? Someone plz xplain which one possible and which one not possible, and why??

asked Nov 29 in Digital Logic by srestha (558 points) | 19 views

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Self Doubt-GATE question
Please check this ques https://gateoverflow.in/1057/gate2004-62 How it could be done in 6 unit time? I think EXOR gate itself need 4 NAND gate. So, And 3 NAND gate is required. Isnot it? Now, 3 AND gate and 2 OR gate required to complete the circuit. Isnot it?

asked Nov 27 in Digital Logic by srestha (558 points) | 17 views

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ACE-NAND GATEs
To design $16$ input NAND gate, the number of $2$ input NAND gate required is ______________ Ans given 29,with a formula 2n-3, but why? I think last level required 8 NAND gate 2nd level required 4 NAND gates Similarly 3rd level 2 and 4th level 1 NAND gates, so, total 15 NAND gates. Where Am I going wrong?

asked Nov 26 in Digital Logic by srestha (558 points) | 16 views

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Digital GATE1993-6.2 Question Doubt.
Source – https://gateoverflow.in/17235/gate1993-6-2 Can someone please explain this question. I am not getting the explanation provided. Thanks!

asked Nov 23 in Digital Logic by iarnav (76 points) | 19 views

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Digitallogic question
How many no of ternary functions are possible with 2 boolean variables? Is this correct logically? I mean with 2 boolean variables we can have functions of just 2 variables at maximum right? Anyone please clarify.

asked Nov 22 in Digital Logic by Shivateja MST (67 points) | 37 views

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Self doubt : In boolean expression simplification
suppose we have something like this: f1(p,q,r) = minterms(1,3,7) f2(p,q,r) = minterms(0,3,6) F = minterms( f1’.f2’ ) = minterms( (1,3,7)’.(0,3,6)’ ) How we simplify this F function directly?

asked Nov 22 in Digital Logic by shaktisingh (87 points) | 19 views

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self doubt: Multiplexer are functionally complete or partially functionally complete

asked Nov 21 in Digital Logic by shaktisingh (87 points) | 18 views

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Self Doubt: r's complement
Is this ans correct? https://gateoverflow.in/235417/ace-test-series-digital-logic-number-system We know that 7's complement of a number is $7777 .- x$ , where x can be any number. And for 8's complement we need to add $1$ with it. Means for ... add 1, Isnot it? Then how in this question ,we are subtracting directly from 8888, which is an even number? Plz someone tell me.

asked Nov 21 in Digital Logic by srestha (558 points) | 14 views

+1 vote

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Success gateway test series
$f_{1}(A,B,C,D)=\Sigma m(0,1,8,9)+\Sigma d(2,10,15)$ $f_{2}(A,B,C,D)=\Sigma m(0,2,9,14)+\Sigma d(1,8,15)$ What is $f_{1}+f_{2}$ and $f_{1}.f_{2}$

asked Nov 20 in Digital Logic by aditi19 (54 points) | 53 views

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UEMK GATE MOCK :DIGITAL
What will be the ans , and how to approach?

asked Nov 16 in Digital Logic by Debapaul (308 points) | 15 views

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Self doubts dld
$F(a,b,c)=F(\bar{a},\bar{b},\bar{c})$ no function possible

asked Nov 13 in Digital Logic by amit166 (113 points) | 12 views

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#DLD How to find delay in Carry look ahead adder?
Ques 1) Exclusive−OR gate has a propagation delay of 10 ns and that the AND or OR gates have a propagation delay of 5 ns.What is the total propagation delay time in the four-bit adder.Assume FAN−IN=2 1) ripple adder 2) ... -ripple-carry Ques 2) https://gateoverflow.in/80674/can-anybody-explain-carry-look-ahead-delay-delay-and-and-and Thank you!

asked Nov 9 in Digital Logic by iarnav (76 points) | 7 views

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GATE GURU 2020: DLD
Minimum number of NOR gates required to implement (A+B+C)’ is_______________ . 4 3 2 5 How to approach these types of question, I always do mistakes in these

asked Nov 4 in Digital Logic by Debapaul (308 points) | 50 views

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GATE CSE GATE Guru:DIGTAL
Consider the function f(a,b,c) = Ʃ(1,3,5,7) + ϕ(0,4). To find the minimal expression for the function f , the don’t cares are treated as 1. 4 is minterm and 0 maxterm 2. Both are maxterms 3. 0 is minterm and 4 maxterm 4. Both are minterms

asked Nov 4 in Digital Logic by Debapaul (308 points) | 22 views

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GATE Guru: DIGITAL LOGIC
I know it is ring counter but what is 2n:1 scale and n:1 scale???

asked Oct 31 in Digital Logic by Debapaul (308 points) | 13 views

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self doubt in boolean algebra
we know that Complement of minterms = maxterms but do this same apply here to:- 1) complement of function of SOP = POS function?Is this right? 2)can we do the complement of X = AB+A’B’ which is SOP to get POS function?

asked Oct 27 in Digital Logic by shaktisingh (87 points) | 22 views

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doubt regarding syllabus of digital logic for gate 2020

asked Oct 26 in Digital Logic by shaktisingh (87 points) | 26 views

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self doubt: What is the CNF if the expression is 0 (zero)?

asked Oct 16 in Digital Logic by commenter commenter (30 points) | 20 views

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Self Doubt: Digital Logic( Boolean Algebra)
Explain the points mentioned in this question. https://gateoverflow.in/60905/ugcnet-june2015-ii-6

asked Oct 14 in Digital Logic by HeartBleed (56 points) | 10 views

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min terms in f' = max terms in f and vice versa. Is this statement true?

asked Oct 14 in Digital Logic by commenter commenter (30 points) | 10 views

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Can someone give summary of all properties/ laws of all digital gates?

asked Oct 13 in Digital Logic by commenter commenter (30 points) | 10 views

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Doubt about Gate 2015 qsn
https://gateoverflow.in/8250/gate2015-2-48 what is the answer of this qsn???? 12 or 19.2 If I follow the formula, the I’l get 19.2 but analyse this problem by drawing ckt diagram & see what happens internally, I’m getting 12 ms. ?????

asked Oct 13 in Digital Logic by MRINMOY_HALDER (37 points) | 17 views

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Gatebook Test Series: Sequence Detector
A sequence detector has to be designed to detect a sequence with at most 3 runs of consecutive zeros of length 3. 001000010001000 This sequence has exactly 2 such runs If we implement a sequential circuit with J-K flip flops then minimum number of flip flops required is ----?

asked Oct 12 in Digital Logic by Lakshman Patel RJIT (104 points) | 24 views

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Gatebook Test Series: Flip Flop and AND Gate
The pattern detected by the above circuit is? 100 010 110 101

asked Oct 11 in Digital Logic by Lakshman Patel RJIT (104 points) | 31 views

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Gatebook Test Series: D Flip Flop

asked Oct 11 in Digital Logic by Lakshman Patel RJIT (104 points) | 30 views

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Gatebook Test Series: Flip Flop

asked Oct 11 in Digital Logic by Lakshman Patel RJIT (104 points) | 20 views

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Gatebook Test Series: Digital Logic - Half Adder

asked Oct 11 in Digital Logic by Lakshman Patel RJIT (104 points) | 22 views

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Gatebook Test Series: Digital Logic - Seven Segment Decoder

asked Oct 11 in Digital Logic by Lakshman Patel RJIT (104 points) | 17 views

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Gatebook Test Series: Digital Logic - Communication Systems

asked Oct 11 in Digital Logic by Lakshman Patel RJIT (104 points) | 19 views

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Virtual gate: Digital

asked Oct 7 in Digital Logic by Kushagra गुप्ता (155 points) | 19 views

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Virtual gate: Digital

asked Oct 7 in Digital Logic by Kushagra गुप्ता (155 points) | 21 views

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Gatebook boolean algebra min - terms
The number of Product terms in SOP Expressions after minimizing the following Boolean expression is: $\bigg[D’+AB’+A’C+AC’D+A’C’D\bigg]$ $1$ $2$ $3$ $4$

asked Oct 4 in Digital Logic by Lakshman Patel RJIT (104 points) | 38 views

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