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Recent questions tagged digitallogic
0
votes
2
answers
Madeeasy Testseries question
III only IV only I, II, III only I, II, IV only Clearly IV is wrong and III is right. I feel I and II need not be true. Anyone please clarify.
asked
1 day
ago
in
Digital Logic
by
Shivateja MST
(
39
points)

29
views
digitallogic
0
votes
1
answer
internet social media
asked
Oct 15
in
Digital Logic
by
Love Barot
(
7
points)

37
views
digitallogic
0
votes
0
answers
Made easy Test Series, Digital Logic, Counters
Hello, I have a doubt here. It is given that we have a cascaded counter with : Counter C1 as Mod 2 counter and C2 as Mod 3 counter. Therefore I can assume that C1 uses 1 flipflop and C2 uses 2 flipflops. Now assuming the ... the solution (it is given 1000 KHz). Can anyone explain me the given solution? How they have arrived at the equation? Thanks!
asked
Sep 21
in
Digital Logic
by
sankalpmittal
(
33
points)

19
views
digitallogic
counters
0
votes
0
answers
Made Easy Test Series, Digital Logic , Combinational Circuits
asked
Sep 21
in
Digital Logic
by
sankalpmittal
(
33
points)

13
views
digitallogic
+1
vote
0
answers
Made Easy Topic Test  2021
Consider the Function f(w,x,y,z) = $\sum m$ (0,4,5,10,14,15 ) + d(7,13) . The number of essential prime implicants are ____ . PS: My answer came out to be 2.
asked
Sep 3
in
Digital Logic
by
dipanjan
(
9
points)

38
views
digitallogic
0
votes
0
answers
Made Easy Topic Test  2021
Determine the Hazard Free SOP Expression for f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD’ + A’C’D + AB’C f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD’ + AB’C’ + A’B’D + A’C’D f(A,B,C,D) = BD + A’B’C’ + ACD + B’CD’ + AB’C
asked
Sep 3
in
Digital Logic
by
dipanjan
(
9
points)

13
views
digitallogic
0
votes
1
answer
GradeUP Test Series
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN, GREEN to RED. In each cycle RED is turned on for 50 seconds, YELLOW is turned on for 40 seconds and GREEN is turned on for 80 seconds. The traffic signal has to be implemented using a ... only input to this FSM is a clock of 10 second period. The minimum number of flip flops required to implement this FSM is _____.
asked
Aug 29
in
Digital Logic
by
Animesh Sinha
(
21
points)

46
views
gradeup
finiteautomata
digitallogic
0
votes
0
answers
Made Easy TopicWise
What does 5 clock triggers mean here? What is the solution?
asked
Aug 28
in
Digital Logic
by
Mellophi
(
333
points)

18
views
madeeasytestseries
digitallogic
0
votes
1
answer
Nptel noc20_ee32_assignment_9 question
asked
Aug 26
in
Digital Logic
by
rana11shubham
(
5
points)

39
views
digitallogic
digitalcounter
0
votes
0
answers
made easy test series 2021
asked
Aug 26
in
Digital Logic
by
rana11shubham
(
5
points)

30
views
digitallogic
logic
digitalcounter
0
votes
2
answers
ME Theory Book
Please explain briefly – how to approach questions like these. Also, few resources where I can learn the concept required to solve such questions. Answer given is – b.
asked
Aug 19
in
Digital Logic
by
Kindaichi
(
15
points)

44
views
gate2021
digitalelectronics
digitallogic
0
votes
0
answers
ME Theory Book
Answer given is – c.
asked
Aug 17
in
Digital Logic
by
Kindaichi
(
15
points)

28
views
gate2021
digitallogic
0
votes
1
answer
TestBook Test series
Answer given is – a.
asked
Aug 17
in
Digital Logic
by
Kindaichi
(
15
points)

21
views
madeeasytestseries
digitallogic
0
votes
1
answer
Madeeasy test
This circuit can work as 4 bit counter D flipflop T flipflop SR flipflop
asked
Aug 16
in
Digital Logic
by
sonam13
(
5
points)

45
views
madeeasytestseries
digitallogic
madeeasytestseries
0
votes
2
answers
Madeeasy test
asked
Aug 16
in
Digital Logic
by
sonam13
(
5
points)

56
views
madeeasytestseries
madeeasytestseries
digitallogic
0
votes
0
answers
shift registers made easy
asked
Aug 15
in
Digital Logic
by
abcd9982
(
87
points)

32
views
madeeasytestseries
digitallogic
shiftregisters
0
votes
0
answers
Madeeasy Test Series
asked
Aug 9
in
Digital Logic
by
Ashish Lakhmani
(
5
points)

31
views
madeeasytestseries
madeeasytestseries
digitallogic
digitalcounter
0
votes
0
answers
Self Doubt: Digital logic design
How many clock pulses required to take input as well as to produce output in each of the following register? a. Serial input Serial output b. Serial input Parallel output c. Parallel input Serial input d. Parallel input Parallel output. ... each register, Please give the no.of clock pulses required for input and no.of clock pulses required for output separately.
asked
Jul 27
in
Digital Logic
by
phaneendrababu
(
17
points)

24
views
digitallogic
0
votes
0
answers
Boolean algebra. Complementation of variables
In boolean logic(DLD) do we always consider a complemented variable as false and a non complemented variable as True? Also while solving problems, can we assume any non complemented variable as 0 and solve? Any help is grealty appreciated (For solving problems in Digital Logic)
asked
Jul 13
in
Digital Logic
by
Pranavapp
(
5
points)

11
views
digitallogic
booleanalgebra
mathematicallogic
0
votes
0
answers
TestBook Test
In an SR latch by crosscoupling two NOR gates if S = 1 and R = 0, then, it’ll result in ___? Can anyone please explain the reason?
asked
Jun 22
in
Digital Logic
by
Jean
(
5
points)

43
views
testbooktestseries
digitallogic
gatepreparation
0
votes
0
answers
MADE EASY TS
I there are 13 flipflops used is PISO shift register circuit, then maximum number of clock cycles required to get the serial output is _____ ?
asked
Jun 9
in
Digital Logic
by
ummokkate
(
39
points)

24
views
digitallogic
madeeasytestseries
0
votes
0
answers
MADE EASY TS
The decimal value of the 2’s complement binary number 11101111110.0010 is ________? I got 130.125, but answer is something else.
asked
Jun 9
in
Digital Logic
by
ummokkate
(
39
points)

26
views
digitallogic
madeeasytestseries
0
votes
1
answer
the gatebook ts
A certain JK FF has a propagation delay of 12ns. The largest MOD of the counter such that, the counter can be designed from these FFs which will operate up to 10 MHz?
asked
Jun 8
in
Digital Logic
by
ummokkate
(
39
points)

25
views
digitallogic
0
votes
0
answers
MADE EASY TS
Here my doubt is that when we get the equation of y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3, given I0, I3 are S1 and I1, I2 are S0 so when we will substitute them, will be substitute y = S1’S0’S1 + S1’S0S0 + S1S0’IS0+ S1S0S1 or will we substitute y = S1’S0’S1’ + S1’S0S0 + S1S0’S0’+ S1S0S1 according to the value of select lines. I’m a bit confused.
asked
Jun 8
in
Digital Logic
by
ummokkate
(
39
points)

17
views
digitallogic
madeeasytestseries
0
votes
1
answer
MADE EASY TS
A function f(x,y,z) = x XNOR y XNOR z = 1, then which of the following is always true? x + yz =1 x not equal to (y XOR z) x.y.z =1 x = y XNOR z I’m getting both option b and option d.
asked
Jun 8
in
Digital Logic
by
ummokkate
(
39
points)

64
views
madeeasytestseries
digitallogic
0
votes
0
answers
THE GATEBOOK TS
Consider the boolean function that has the don't care states: and . How many prime implicants (P) and essential prime implicants (EP) are there for F? (A). Five (P) and Three (EP) (B). Four (P) and Three (EP) (C). Five (P) and Two (EP) (D). Six ... Three (EP) I'm getting option B, but answer given is option A. Reason given is don't cares will also make 1 PI, can anyone confirm it.
asked
Jun 7
in
Digital Logic
by
ummokkate
(
39
points)

15
views
digitallogic
kmap
+2
votes
0
answers
Self doubt on GB: Digital Logic
When two 8bit numbers and in 2's complement representation (with and as the least significant bits) are subtracted(i.e. AB) by first negating the subtrahend and then adding it to the minuend using a ripplecarry adder, the sum bits obtained are and the carry ... 1 (B). is 1 (C). is 1 (D). is 1 How this question will differ from previous GATE question? Plz verify
asked
Jun 1
in
Digital Logic
by
srestha
(
1k
points)

26
views
digitallogic
0
votes
0
answers
How we got exponent as $2^{12764}$?
Information: Consider a 16bit register of the following format is used to store a floating point number. Mantissa (M) is denoted as normalized signed magnitude fraction, Exponent (E) is expressed in excess64 form. Base of the system is ... ? Please explain it as you are explaining to naive person. I am missing something very obvious! Waiting for explanation!
asked
Apr 24
in
Digital Logic
by
ubibhatt
(
5
points)

14
views
floatingpoint
digitallogic
0
votes
0
answers
GATE19891vi
It would be helpful if you provide me the solution. i'm not able to understand the solution which is given in go site. please provide me detailed explanation GATE19891vi Consider an excess  50 representation for floating point ... digit exponent in normalised form. The minimum and maximum positive numbers that can be represented are __________ and _____________ respectively.
asked
Apr 20
in
Digital Logic
by
varunraj
(
5
points)

17
views
numberrepresentation
digitallogic
floatingpointrepresentation
0
votes
0
answers
GATE199202ii
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: All digital circuits can be realized using only A.ExOR gates B.Multiplexers C.Half adders D.OR gates I have a doubt in question ... complete or partially functionally complete? multiplexer and Half adders are partially functionally complete.WHAT IS THE ACTUAL ANSWER??????
asked
Apr 19
in
Digital Logic
by
varunraj
(
5
points)

14
views
functionalcompleteness
digitallogic
adder
multiplexer
0
votes
0
answers
GATE20068 digital logic
please explain me the solution and how to draw timing diagrams for this kind of questions?
asked
Apr 19
in
Digital Logic
by
varunraj
(
5
points)

8
views
digitallogic
flipflop
frequency
clocktime
clockfrequency
0
votes
0
answers
GATE201618 Video Solution
We want to design a synchronous counter that counts the sequence $010203$ and then repeats. The minimum number of $\text{JK}$ flipflops required to implement this counter is _____________.
asked
Apr 18
in
Digital Logic
by
admin
(
193
points)

11
views
gate20161
digitallogic
digitalcounter
flipflop
normal
numericalanswers
videosolution
0
votes
1
answer
GATE2015248 Video Solution
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is ... binary adder is implemented by using four full adders. The total propagation time of this 4bit binary adder in microseconds is ______.
asked
Apr 18
in
Digital Logic
by
admin
(
193
points)

28
views
gate20152
digitallogic
adder
normal
numericalanswers
videosolution
0
votes
0
answers
GATE201527 Video Solution
The minimum number of JK flipflops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is _______.
asked
Apr 18
in
Digital Logic
by
admin
(
193
points)

9
views
gate20152
digitallogic
digitalcounter
normal
numericalanswers
videosolution
0
votes
0
answers
GATE2016133 Video Solution
Consider a carry look ahead adder for adding two nbit integers, built using gates of fanin at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
asked
Apr 18
in
Digital Logic
by
admin
(
193
points)

7
views
gate20161
digitallogic
adder
normal
videosolution
0
votes
0
answers
GATE200462 Video Solution
A 4bit carry look ahead adder, which adds two 4bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time ... the carry network has been implemented using twolevel ANDOR logic. 4 time units 6 time units 10 time units 12 time units
asked
Apr 18
in
Digital Logic
by
admin
(
193
points)

9
views
gate2004
digitallogic
normal
adder
videosolution
0
votes
0
answers
GATE200734 Video Solution
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n1}$ line to $1$line $2^{n2}$ line to $1$line
asked
Apr 18
in
Digital Logic
by
admin
(
193
points)

7
views
gate2007
digitallogic
normal
multiplexer
videosolution
0
votes
0
answers
GATE200638 Video Solution
Consider a Boolean function $ f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $ i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle $ ... $ wx\overline{y} \overline{z}, xz, w\overline{x}yz$ $ wx\overline{y}, wyz, wxz, \overline{w}xz, x\overline{y}z, xyz$
asked
Apr 18
in
Digital Logic
by
admin
(
193
points)

8
views
gate2006
digitallogic
minsumofproductsform
difficult
statichazard
videosolution
0
votes
0
answers
GATE201032 Video Solution
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$ $10$, $11$, $01$, $00$ $10$, $00$, $01$, $11$ $11$, $10$, $00$, $01$
asked
Apr 18
in
Digital Logic
by
admin
(
193
points)

4
views
gate2010
digitallogic
circuitoutput
normal
videosolution
0
votes
0
answers
GATE2017212 Video Solution
Given the following binary number in $32$bit (single precision) $IEEE754$ format : $\large 00111110011011010000000000000000$ The decimal value closest to this floatingpoint number is : $1.45*10^1$ $1.45*10^{1}$ $2.27*10^{1}$ $2.27*10^1$
asked
Apr 18
in
Digital Logic
by
admin
(
193
points)

6
views
gate20172
digitallogic
numberrepresentation
floatingpointrepresentation
ieeerepresentation
videosolution
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