Recent questions tagged normal - GATE CSE Doubts

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GATE2008-67 Video Solution
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as ... tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$

asked Apr 18 in Operating System by admin (197 points) | 88 views

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GATE2004-47 Video Solution
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. ... execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$

asked Apr 18 in CO & Architecture by admin (197 points) | 26 views

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GATE2016-1-8 Video Solution
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.

asked Apr 18 in Digital Logic by admin (197 points) | 12 views

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GATE2009-57, ISRO2016-75 Video Solution
Frames of $\text{1000 bits}$ are sent over a $10^6$ $\text{bps}$ duplex link between two hosts. The propagation time is $\text{25 ms}$. Frames are to be transmitted into this link to maximally pack them in transit (within the link). What is the ... ? Assume that no time gap needs to be given between transmission of two frames. $I=2$ $I=3$ $I=4$ $I=5$

asked Apr 18 in Computer Networks by admin (197 points) | 15 views

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GATE2005-68 Video Solution
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$

asked Apr 18 in CO & Architecture by admin (197 points) | 20 views

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GATE2013-45 Video Solution
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$

asked Apr 18 in CO & Architecture by admin (197 points) | 29 views

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GATE2014-1-39 Video Solution
The minimum number of comparisons required to find the minimum and the maximum of $100$ numbers is ________

asked Apr 18 in Algorithms by admin (197 points) | 11 views

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GATE2015-2-48 Video Solution
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is ... binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.

asked Apr 18 in Digital Logic by admin (197 points) | 31 views

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GATE2003-78 Video Solution
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the ... virtual address is approximately (to the nearest $0.5$ ns) $1.5$ ns $2$ ns $3$ ns $4$ ns

asked Apr 18 in Operating System by admin (197 points) | 10 views

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GATE2015-2-7 Video Solution
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is _______.

asked Apr 18 in Digital Logic by admin (197 points) | 9 views

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GATE2013-52 Video Solution
A computer uses $46-bit$ virtual address, $32-bit$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $(T1)$, which occupies exactly one page. Each entry of $T1$ stores the base address ... size is $64$ bytes. What is the size of a page in $KB$ in this computer? $2$ $4$ $8$ $16$

asked Apr 18 in Operating System by admin (197 points) | 10 views

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GATE2016-2-40 Video Solution
The number of ways in which the numbers $1, 2, 3, 4, 5, 6, 7$ can be inserted in an empty binary search tree, such that the resulting tree has height $6$, is _________. Note: The height of a tree with a single node is $0$.

asked Apr 18 in DS by admin (197 points) | 14 views

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GATE2005-70 Video Solution
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent ... $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$

asked Apr 18 in CO & Architecture by admin (197 points) | 5 views

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GATE2016-1-54 Video Solution
For a host machine that uses the token bucket algorithm for congestion control, the token bucket has a capacity of $1$ $\text{megabyte}$ and the maximum output rate is $20$ $\text{megabytes}$ per $\text{second}$. Tokens arrive at a rate to ... to send $12$ $\text{megabytes}$ of data. The minimum time required to transmit the data is _____________ $\text{seconds}$.

asked Apr 18 in Computer Networks by admin (197 points) | 11 views

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GATE2017-1-51 Video Solution
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due ... $10$ times. The number of conflict misses experienced by the cache is _________ .

asked Apr 18 in CO & Architecture by admin (197 points) | 32 views

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GATE2007-IT-29 Video Solution
When searching for the key value $60$ in a binary search tree, nodes containing the key values $10, 20, 40, 50, 70, 80, 90$ are traversed, not necessarily in the order given. How many different orders are possible in which these key values can occur on the search path from the root to the node containing the value $60$? $35$ $64$ $128$ $5040$

asked Apr 18 in DS by admin (197 points) | 7 views

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GATE2012-45 Video Solution
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of the slow start phase is $2$ MSS and the threshold at the start of the first transmission is $8$ MSS. Assume that a timeout occurs during ... . Find the congestion window size at the end of the tenth transmission. $8$ MSS $14$ MSS $7$ MSS $12$ MSS

asked Apr 18 in Computer Networks by admin (197 points) | 9 views

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GATE2010-48 Video Solution
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ ... ? $2 \hspace{0.1cm} nanoseconds$ $20 \hspace{0.1cm} nanoseconds$ $22 \hspace{0.1cm}nanoseconds$ $88 \hspace{0.1cm} nanoseconds$

asked Apr 18 in CO & Architecture by admin (197 points) | 7 views

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GATE2014-1-27 Video Solution
Let the size of congestion window of a TCP connection be $32$ KB when a timeout occurs. The round trip time of the connection is $100$ msec and the maximum segment size used is $2$ KB. The time taken (in msec) by the TCP connection to get back to $32$ KB congestion window is _________.

asked Apr 18 in Computer Networks by admin (197 points) | 7 views

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GATE2004-IT-12, ISRO2016-77 Video Solution
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rates of Level $1$ and Level $2$ caches are $0.8$ and $0.9$, respectively. What is the average access time of the system ignoring the search time within the cache? $13.0$ $12.8$ $12.6$ $12.4$

asked Apr 18 in CO & Architecture by admin (197 points) | 9 views

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GATE2001-2.23 Video Solution
$R(A,B,C,D)$ is a relation. Which of the following does not have a lossless join, dependency preserving $BCNF$ decomposition? $A \rightarrow B, B \rightarrow CD$ $A \rightarrow B, B \rightarrow C, C \rightarrow D$ $ AB \rightarrow C, C \rightarrow AD$ $A \rightarrow BCD$

asked Apr 18 in Databases by admin (197 points) | 7 views

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GATE2016-1-39 Video Solution
Let $G$ be a complete undirected graph on $4$ vertices, having $6$ edges with weights being $1, 2, 3, 4, 5,$ and $6$. The maximum possible weight that a minimum weight spanning tree of $G$ can have is __________

asked Apr 18 in Algorithms by admin (197 points) | 3 views

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GATE2008-46 Video Solution
You are given the postorder traversal, $P$, of a binary search tree on the $n$ elements $1, 2, \dots, n$. You have to determine the unique binary search tree that has $P$ as its postorder traversal. What is the time complexity of the most efficient algorithm ... $\Theta(\log n)$ $\Theta(n)$ $\Theta(n\log n)$ None of the above, as the tree cannot be uniquely determined

asked Apr 18 in DS by admin (197 points) | 8 views

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GATE2012-38 Video Solution
Let $G$ be a complete undirected graph on $6$ vertices. If vertices of $G$ are labeled, then the number of distinct cycles of length $4$ in $G$ is equal to $15$ $30$ $90$ $360$

asked Apr 18 in Graph Theory by admin (197 points) | 14 views

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GATE2008-IT-61 Video Solution
Let $R (A, B, C, D)$ be a relational schema with the following functional dependencies : $A → B$, $B → C$, $C → D$ and $D → B$. The decomposition of $R$ into $(A, B), (B, C), (B, D)$ gives a ... a lossless join, but is not dependency preserving does not give a lossless join, but is dependency preserving does not give a lossless join and is not dependency preserving

asked Apr 18 in Databases by admin (197 points) | 8 views

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GATE2015-3-36 Video Solution
Two hosts are connected via a packet switch with $10^7$ bits per second links. Each link has a propagation delay of $20$ microseconds. The switch begins forwarding a packet $35$ microseconds after it receives the same. If $10000$ bits of data ... between the transmission of the first bit of data and the reception of the last bit of the data in microseconds is ______.

asked Apr 18 in Computer Networks by admin (197 points) | 9 views

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GATE2015-1-46 Video Solution
Consider a uniprocessor system executing three tasks $T_{1}, T_{2}$ and $T_{3}$ each of which is composed of an infinite sequence of jobs (or instances) which arrive periodically at intervals of $3$, $7$ and $20$ ... 1st millisecond and task preemptions are allowed, the first instance of $T_{3}$ completes its execution at the end of_____________________milliseconds.

asked Apr 18 in Operating System by admin (197 points) | 8 views

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GATE2017-1-45 Video Solution
The values of parameters for the Stop-and-Wait ARQ protocol are as given below: Bit rate of the transmission channel = $1$ Mbps. Propagation delay from sender to receiver = $0.75$ ms. Time to process a frame = $0.25$ ms. Number of ... (expressed in percentage) of the Stop-and-Wait ARQ protocol for the above parameters is _____________ (correct to $2$ decimal places).

asked Apr 18 in Computer Networks by admin (197 points) | 6 views

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GATE2014-2-47 Video Solution
The product of the non-zero eigenvalues of the matrix is ____ $\begin{pmatrix} 1 & 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 1 & 0 \\ 0 & 1 & 1 & 1 & 0 \\ 0 & 1 & 1 & 1 & 0 \\ 1 & 0 & 0 & 0 & 1 \end{pmatrix}$

asked Apr 18 in Linear Algebra by admin (197 points) | 15 views

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GATE2016-2-15 Video Solution
$N$ items are stored in a sorted doubly linked list. For a delete operation, a pointer is provided to the record to be deleted. For a decrease-key operation, a pointer is provided to the record on which the operation is to be performed. An algorithm performs the following operations on the ... together? $O(\log^{2} N)$ $O(N)$ $O(N^{2})$ $\Theta\left(N^{2}\log N\right)$

asked Apr 18 in DS by admin (197 points) | 18 views

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GATE2005-65 Video Solution
Consider a three word machine instruction $ADD A[R_0], @B$ The first operand (destination) $A[R_0]$ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) [email protected]$ uses indirect addressing mode. $A$ and $B$ are ... (first operand). The number of memory cycles needed during the execution cycle of the instruction is: $3$ $4$ $5$ $6$

asked Apr 18 in CO & Architecture by admin (197 points) | 9 views

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GATE2009-28 Video Solution
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below: $\begin{array}{|c|c|c|c|c|} \hline \textbf{} & \textbf {$S _1$} &\textbf {$ ... number of cycles needed to execute the following loop? For $(i=1$ to $2)$ {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

asked Apr 18 in CO & Architecture by admin (197 points) | 8 views

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GATE2014-3-39 Video Solution
Suppose we have a balanced binary search tree $T$ holding $n$ numbers. We are given two numbers $L$ and $H$ and wish to sum up all the numbers in $T$ that lie between $L$ and $H$. Suppose there are $m$ such numbers in $T$. If the tightest upper bound on the time to compute the sum is $O(n^a\log^bn+m^c\log^dn)$, the value of $a+10b+100c+1000d$ is ______.

asked Apr 18 in DS by admin (197 points) | 31 views

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GATE2016-1-33 Video Solution
Consider a carry look ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)

asked Apr 18 in Digital Logic by admin (197 points) | 7 views

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GATE2016-1-19 Video Solution
Consider the following code segment. x = u - t; y = x * v; x = y + w; y = t - z; y = x * y; The minimum number of total variables required to convert the above code segment to static single assignment form is __________.

asked Apr 18 in Compiler Design by admin (197 points) | 7 views

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GATE1994-1.6, ISRO2008-29 Video Solution
The number of distinct simple graphs with up to three nodes is $15$ $10$ $7$ $9$

asked Apr 18 in Graph Theory by admin (197 points) | 5 views

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GATE2017-1-27 Video Solution
A multithreaded program $P$ executes with $x$ number of threads and uses $y$ number of locks for ensuring mutual exclusion while operating on shared memory locations. All locks in the program are non-reentrant, i.e., if a thread holds a lock $l$, then it cannot re-acquire lock $l$ without releasing it. If ... : $x = 1, y = 2$ $x = 2, y = 1$ $x = 2, y = 2$ $x = 1, y = 1$

asked Apr 18 in Operating System by admin (197 points) | 4 views

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GATE2013-39 Video Solution
A certain computation generates two arrays a and b such that $a[i] = f(i)$ for $0 \leq i < n$ and $b[i] = g(a[i])$ for $0 \leq i < n$. Suppose this computation is decomposed into two concurrent processes $X$ and $Y$ such that $X$ computes the array $a$ and $Y$ computes the ... EntryY(R, S) { V(S); P(R); } ExitX(R, S) { V(R); P(S); } EntryY(R, S) { V(S); P(R); }

asked Apr 18 in Operating System by admin (197 points) | 9 views

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GATE2012-32 Video Solution
Fetch_And_Add(X,i) is an atomic Read-Modify-Write instruction that reads the value of memory location $X$, increments it by the value $i$, and returns the old value of $X$. It is used in the pseudocode shown below to implement ... take on a non-zero value when the lock is actually available works correctly but may starve some processes works correctly without starvation

asked Apr 18 in Operating System by admin (197 points) | 16 views

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GATE2005-73 Video Solution
In a packet switching network, packets are routed from source to destination along a single path having two intermediate nodes. If the message size is $24$ bytes and each packet contains a header of $3$ bytes, then the optimum packet size is: $4$ $6$ $7$ $9$

asked Apr 18 in Computer Networks by admin (197 points) | 4 views

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