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Recent questions tagged paging
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#paging #operatingsystem #gateCSE #gateOperatingSystem
asked
Feb 21
in
Operating System
by
cheNavya
(
5
points)
|
12
views
paging
0
votes
1
answer
IIT Bombay website
Consider a system with a 6 bit virtual address space, and 16 byte pages/frames. The mapping from virtual page numbers to physical frame numbers of a process is (0,8), (1,3), (2,11), and (3,1). Translate the following virtual addresses to physical addresses. Note ... or binary. (a) 20 (b) 40 Source:https://www.cse.iitb.ac.in/~mythili/os/ps/memory/ps-memory.pdf (Question-19)
asked
Feb 6
in
Operating System
by
shantanu4raje
(
25
points)
|
25
views
operatingsystem
paging
0
votes
0
answers
Applied Mock Test
Find the Effective Time
asked
Jan 26
in
Operating System
by
Sahil91
(
683
points)
|
18
views
paging
0
votes
0
answers
#MadeEasyTestSeries
In a demand paging system with a paging disk that has an average access and transfer time of 45 milliseconds. Address are mapped through a page table in main memory, with an access time of 75 us per memory access. An associative memory (TLB) is added to reduce ... in this question we have consider 2 micro sec for TLBmiss i.e. (1+1) i.e page table acccess+main memory access time
asked
Dec 11, 2020
in
Operating System
by
rupesh17
(
5
points)
|
7
views
paging
0
votes
0
answers
Applied Test Series-OS
Consider a system using a segmented paging architecture. The segment is divided into 8k pages each of size 2k words . The segment table is divided into 256 k pages each of size 512 words. The page table entry size requires 64 bits . The frame number requires 22 bits ... +24) Segment No-(24) Offset(24) segment no= (256K*512B)/8B Offset = 8K*2KB. Please Correct me if am wrong.
asked
Nov 15, 2020
in
Operating System
by
Sahil91
(
683
points)
|
43
views
operatingsystem
paging
segmentation
0
votes
0
answers
Trishna Knowledge Systems Practice Tests
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and cache access are sequential. ... memory access latencies when the cache is physically addresses (in cycles). A) 2.45 B) 9.35 C) 15.75 D) 18.25
asked
Nov 10, 2020
in
Operating System
by
SarathBaswa
(
849
points)
|
14
views
virtual-memory
tlb
paging
0
votes
1
answer
Made Easy Test Series - OS: Paging
I think the answer should be 22 MB. We get Page Table Entry size = (22/8) B Page table size = 2^23 * 22/8 B = 22 MB. Why have they rounded 22/8 as 3B? Answer should be 22 MB and not 24 MB. Please clarify. Thanks!
asked
Sep 8, 2020
in
Operating System
by
sankalpmittal
(
41
points)
|
43
views
operating-system
made-easy-test-series
memory-management
paging
0
votes
0
answers
Made Easy - Memory management and Paging
#OS Memory Management Question on Paging and Translation Look-aside Buffer (TLB)
asked
Aug 29, 2020
in
Operating System
by
dhruvikk6
(
5
points)
|
27
views
operating-system
memory-management
paging
tlb
0
votes
1
answer
#made easy test series
consider a system using 2 level paging and virtual address is 38 bits.the most significant 10 bits are used to index the page directory and next 16 bits index the page table.Each entry in both levels in 4 bytes .what is the maximum number of page tables that a process can have__? it’s answer is given as 1024
asked
Aug 9, 2020
in
Operating System
by
404 found
(
37
points)
|
322
views
operating-system
madeeasytestseries
paging
0
votes
0
answers
4 Level Page Table Doubt. (Udacity lecture: "4 Level PT Solution Quiz - Georgia Tech - HPCA: Part 4")
asked
Aug 1, 2020
in
Operating System
by
RasMalai
(
27
points)
|
26
views
operating-system
paging
selfdoubt
0
votes
0
answers
Multilevel Paging: Gradeup exercise Problem
consider a s/m using 2 level paging where IPT divided into 512 pages each 2K bytes. if PAS divided into 512 frames with supported PA of 21 bits. calculate the size of TOTAL LAS & also size of OPT & IPT if PT Entires are 2B each
asked
Jul 29, 2020
in
Operating System
by
Sgr007
(
21
points)
|
35
views
multilevel
paging
0
votes
0
answers
#Doubt Gate 2003-26
In this pqy : https://gateoverflow.in/916/gate2003-26, the selected answer says that there is no external fragmentation. Since it is only 1 level paging and the page table size after calculation is greater than page size, so it can't be ... page size and thus causes external fragmentation. So, shouldn't the translation not be possible because of external frag at first place.
asked
Jul 17, 2020
in
Operating System
by
pranavsettaluri9
(
5
points)
|
24
views
operating-system
virtual-memory
paging
0
votes
0
answers
Operating system
Can anyone summarise all the possible formulas regarding Tlb (involving pagefaults,cache,dirty write etc)
asked
Jun 14, 2020
in
Operating System
by
sreejit007
(
5
points)
|
11
views
operating-system
paging
0
votes
0
answers
memory management application
Consider a movie player application that supports functions like play movie, skip forward x frames and skip backward x frames. Suggest a memory management policy that will be best suited for this application. (source: question 4.4 ) Ans is given as: A ... if we use Look-ahead as in paging, then this will perform equally well, if not better. Please comment on it.
asked
Jun 5, 2020
in
Operating System
by
reboot
(
5
points)
|
32
views
memory-management
operating-system
segmentation
paging
virtual-memory
0
votes
1
answer
Operating System Concepts (9th Ed) - Gagne, Silberschatz, and Galvin
asked
May 22, 2020
in
Operating System
by
kayes360
(
5
points)
|
43
views
operating-system
threads
multi-processor
process-synchronization
paging
0
votes
1
answer
GATE2014_set2_33
Gate2014 set 2 question 33 In this question demand paging is not mentioned,but the answer used it.In MRU non referenced frames are replaced first and then MRU works???
asked
Apr 28, 2020
in
Operating System
by
ananya207
(
5
points)
|
29
views
paging
operating-system
mru
page-replacement
0
votes
0
answers
Memory Mangement #OS#GATE
In demand paging system CPU Utilization 20% Paging Disk 97.7% Other I/O device 5% Which will probably improve CPU Utilization? Increase the degree of multiprogramming Decrease the degree of multiprogramming Increase the page size None of these. Please explain.
asked
Apr 16, 2020
in
Operating System
by
sushmitagoswami
(
5
points)
|
56
views
paging
operating-system
0
votes
0
answers
Operating System
Suppose that a disk drive has 5,000 cylinders, numbered 0 to 4999. The drive is currently serving a request at cylinder 143, and the previous request was at cylinder 125. The queue of pending requests, in FIFO order, is: 86,1470, 913, 1774, ... what is the total distance (in cylinders) that the disk arm moves to satisfy all the pending requests for SCAN disk scheduling algorithm?
asked
Apr 11, 2020
in
Operating System
by
unknown_a
(
5
points)
|
75
views
operating-system
paging
0
votes
1
answer
page table access
What is the mode(User/Kernel) of the Operating System when a Page Table or TLB are being accessed?
asked
Mar 18, 2020
in
Operating System
by
smsubham
(
33
points)
|
20
views
operating-system
paging
selfdoubt
0
votes
0
answers
No bits in Frames
Account for the validity and justification about the correctness of this statement " Whatever level page table is always the number of bits which are going to refer a frame number will always going to be same "
asked
Mar 18, 2020
in
Operating System
by
smsubham
(
33
points)
|
7
views
operating-system
paging
0
votes
1
answer
gate practice papers
Conventional page table has ‘m’ entries and an Inverted page table has ‘n’ entries, Main memory access time is ‘k’ ns, the worst case time requirement for address translation using conventional paging and inverted paging is _____ and _____ respectively
asked
Feb 27, 2020
in
Operating System
by
dheeraj2310
(
5
points)
|
42
views
paging
memory
+1
vote
2
answers
Self Doubt : Operating System
What is default page size of 32 and 64 bit WINDOWS OS?
asked
Feb 15, 2020
in
Operating System
by
Chirag Shilwant
(
191
points)
|
41
views
operating-system
paging
page-size
0
votes
0
answers
Multi-Level Paging
How many levels of paging is required such that outer page table fits in one page size assuming page size=4 KB and page table entry size=4 B at all levels and logical address=64 bits?
asked
Feb 4, 2020
in
Operating System
by
Srush
(
5
points)
|
58
views
operating-system
paging
multilevel
0
votes
0
answers
RBR Test Series
asked
Dec 11, 2019
in
Operating System
by
Priyansh Singh
(
227
points)
|
46
views
paging
0
votes
0
answers
self doubt-demand paging and virtual memory
1>Can demand paging exists without virtual memery? 2>And is virtual memory of any use without demand paging?
asked
Nov 26, 2019
in
Operating System
by
Doraemon
(
65
points)
|
23
views
operating-system
paging
0
votes
0
answers
TLB with demand paging
Formula 1 EAT with page fault in demand paging = Page fault rate * {Effective Access Time without page fault + Page fault service time} + (1 - Page fault rate) * {Effective Access time without page fault} Where, Effective Access Time without ... while solving questions ? I am getting confused when to apply which formula. According to me we should always use formula 1.
asked
Nov 13, 2019
in
Operating System
by
Satbir
(
6.9k
points)
|
235
views
operating-system
demand
paging
0
votes
0
answers
Segmented paging Self Doubt
In segmented paging the logical address space of a program is divided into variable sized segments. Further the segments are divided into fixed size pages The page sizes of different segments are same or different?
asked
Sep 13, 2019
in
Operating System
by
aditi19
(
53
points)
|
50
views
operating-system
segmentation
page
paging
segmented-paging
0
votes
3
answers
http://www.cs.utexas.edu/~lorenzo/corsi/cs372/06F/hw/3sol.html
asked
Sep 9, 2019
in
Operating System
by
chirudeepnamini
(
9
points)
|
179
views
operating-system
multilevel
paging
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