Recent questions tagged paging - GATE CSE Doubts

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Operation system self dout
Q. consider a system with 2k pages ,512 frames ,pa=22 bits. calculate the page table size in bytes?

asked Apr 28 in Operating System by Enolx.21 (49 points) | 20 views

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https://www.cs.utexas.edu/~lorenzo/corsi/cs372/06F/hw/3sol.html

asked Apr 13 in Operating System by Pranavapp (5 points) | 20 views

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https://www.cs.utexas.edu/~lorenzo/corsi/cs372/06F/hw/3sol.html

asked Apr 13 in Operating System by Pranavapp (5 points) | 14 views

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Simple-paging
What happen if page size and frame size are not equal? will it failed to map logical address to physical address.

asked Mar 28 in Operating System by Biswanath (5 points) | 32 views

+2 votes

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Paging. Self-Doubt
Here I solved this in this way .. Since the virtual address space is 32-bit long and the first 8 bit specifies the first-level index. Next is the Offset of the page which is 12 from the first line. Coincidently, 20 bit are still left here and it ... this might be the answer. For reference, the answer to the solution is given . Thanks in advance. Is my approach wrong or correct?

asked Mar 20 in Operating System by kirtipurohit (15 points) | 19 views

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#paging #operatingsystem #gateCSE #gateOperatingSystem

asked Feb 21 in Operating System by cheNavya (5 points) | 16 views

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IIT Bombay website
Consider a system with a 6 bit virtual address space, and 16 byte pages/frames. The mapping from virtual page numbers to physical frame numbers of a process is (0,8), (1,3), (2,11), and (3,1). Translate the following virtual addresses to physical addresses. Note ... or binary. (a) 20 (b) 40 Source:https://www.cse.iitb.ac.in/~mythili/os/ps/memory/ps-memory.pdf (Question-19)

asked Feb 6 in Operating System by shantanu4raje (25 points) | 54 views

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Applied Mock Test
Find the Effective Time

asked Jan 26 in Operating System by Sahil91 (683 points) | 21 views

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#MadeEasyTestSeries
In a demand paging system with a paging disk that has an average access and transfer time of 45 milliseconds. Address are mapped through a page table in main memory, with an access time of 75 us per memory access. An associative memory (TLB) is added to reduce ... in this question we have consider 2 micro sec for TLBmiss i.e. (1+1) i.e page table acccess+main memory access time

asked Dec 11, 2020 in Operating System by rupesh17 (5 points) | 9 views

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Applied Test Series-OS
Consider a system using a segmented paging architecture. The segment is divided into 8k pages each of size 2k words . The segment table is divided into 256 k pages each of size 512 words. The page table entry size requires 64 bits . The frame number requires 22 bits ... +24) Segment No-(24) Offset(24) segment no= (256K*512B)/8B Offset = 8K*2KB. Please Correct me if am wrong.

asked Nov 15, 2020 in Operating System by Sahil91 (683 points) | 77 views

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Trishna Knowledge Systems Practice Tests
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and cache access are sequential. ... memory access latencies when the cache is physically addresses (in cycles). A) 2.45 B) 9.35 C) 15.75 D) 18.25

asked Nov 10, 2020 in Operating System by SarathBaswa (849 points) | 16 views

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Made Easy Test Series - OS: Paging
I think the answer should be 22 MB. We get Page Table Entry size = (22/8) B Page table size = 2^23 * 22/8 B = 22 MB. Why have they rounded 22/8 as 3B? Answer should be 22 MB and not 24 MB. Please clarify. Thanks!

asked Sep 8, 2020 in Operating System by sankalpmittal (41 points) | 45 views

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Made Easy - Memory management and Paging
#OS Memory Management Question on Paging and Translation Look-aside Buffer (TLB)

asked Aug 29, 2020 in Operating System by dhruvikk6 (5 points) | 28 views

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#made easy test series
consider a system using 2 level paging and virtual address is 38 bits.the most significant 10 bits are used to index the page directory and next 16 bits index the page table.Each entry in both levels in 4 bytes .what is the maximum number of page tables that a process can have__? it’s answer is given as 1024

asked Aug 9, 2020 in Operating System by 404 found (37 points) | 355 views

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4 Level Page Table Doubt. (Udacity lecture: "4 Level PT Solution Quiz - Georgia Tech - HPCA: Part 4")

asked Aug 1, 2020 in Operating System by RasMalai (27 points) | 29 views

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Multilevel Paging: Gradeup exercise Problem
consider a s/m using 2 level paging where IPT divided into 512 pages each 2K bytes. if PAS divided into 512 frames with supported PA of 21 bits. calculate the size of TOTAL LAS & also size of OPT & IPT if PT Entires are 2B each

asked Jul 29, 2020 in Operating System by Sgr007 (21 points) | 36 views

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#Doubt Gate 2003-26
In this pqy : https://gateoverflow.in/916/gate2003-26, the selected answer says that there is no external fragmentation. Since it is only 1 level paging and the page table size after calculation is greater than page size, so it can't be ... page size and thus causes external fragmentation. So, shouldn't the translation not be possible because of external frag at first place.

asked Jul 17, 2020 in Operating System by pranavsettaluri9 (5 points) | 26 views

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Operating system
Can anyone summarise all the possible formulas regarding Tlb (involving pagefaults,cache,dirty write etc)

asked Jun 14, 2020 in Operating System by sreejit007 (5 points) | 13 views

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memory management application
Consider a movie player application that supports functions like play movie, skip forward x frames and skip backward x frames. Suggest a memory management policy that will be best suited for this application. (source: question 4.4 ) Ans is given as: A ... if we use Look-ahead as in paging, then this will perform equally well, if not better. Please comment on it.

asked Jun 5, 2020 in Operating System by reboot (5 points) | 38 views

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Operating System Concepts (9th Ed) - Gagne, Silberschatz, and Galvin

asked May 22, 2020 in Operating System by kayes360 (5 points) | 50 views

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GATE2014_set2_33
Gate2014 set 2 question 33 In this question demand paging is not mentioned,but the answer used it.In MRU non referenced frames are replaced first and then MRU works???

asked Apr 28, 2020 in Operating System by ananya207 (5 points) | 31 views

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Memory Mangement #OS#GATE
In demand paging system CPU Utilization 20% Paging Disk 97.7% Other I/O device 5% Which will probably improve CPU Utilization? Increase the degree of multiprogramming Decrease the degree of multiprogramming Increase the page size None of these. Please explain.

asked Apr 16, 2020 in Operating System by sushmitagoswami (5 points) | 58 views

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Operating System
Suppose that a disk drive has 5,000 cylinders, numbered 0 to 4999. The drive is currently serving a request at cylinder 143, and the previous request was at cylinder 125. The queue of pending requests, in FIFO order, is: 86,1470, 913, 1774, ... what is the total distance (in cylinders) that the disk arm moves to satisfy all the pending requests for SCAN disk scheduling algorithm?

asked Apr 11, 2020 in Operating System by unknown_a (5 points) | 112 views

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page table access
What is the mode(User/Kernel) of the Operating System when a Page Table or TLB are being accessed?

asked Mar 18, 2020 in Operating System by smsubham (33 points) | 21 views

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No bits in Frames
Account for the validity and justification about the correctness of this statement " Whatever level page table is always the number of bits which are going to refer a frame number will always going to be same "

asked Mar 18, 2020 in Operating System by smsubham (33 points) | 9 views

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1 answer

gate practice papers
Conventional page table has ‘m’ entries and an Inverted page table has ‘n’ entries, Main memory access time is ‘k’ ns, the worst case time requirement for address translation using conventional paging and inverted paging is _____ and _____ respectively

asked Feb 27, 2020 in Operating System by dheeraj2310 (5 points) | 47 views

+1 vote

2 answers

Self Doubt : Operating System
What is default page size of 32 and 64 bit WINDOWS OS?

asked Feb 15, 2020 in Operating System by Chirag Shilwant (191 points) | 43 views

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Multi-Level Paging
How many levels of paging is required such that outer page table fits in one page size assuming page size=4 KB and page table entry size=4 B at all levels and logical address=64 bits?

asked Feb 4, 2020 in Operating System by Srush (5 points) | 60 views

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RBR Test Series

asked Dec 11, 2019 in Operating System by Priyansh Singh (227 points) | 53 views

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self doubt-demand paging and virtual memory
1>Can demand paging exists without virtual memery? 2>And is virtual memory of any use without demand paging?

asked Nov 26, 2019 in Operating System by Doraemon (69 points) | 25 views

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TLB with demand paging
Formula 1 EAT with page fault in demand paging = Page fault rate * {Effective Access Time without page fault + Page fault service time} + (1 - Page fault rate) * {Effective Access time without page fault} Where, Effective Access Time without ... while solving questions ? I am getting confused when to apply which formula. According to me we should always use formula 1.

asked Nov 13, 2019 in Operating System by Satbir (7k points) | 251 views

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Segmented paging Self Doubt
In segmented paging the logical address space of a program is divided into variable sized segments. Further the segments are divided into fixed size pages The page sizes of different segments are same or different?

asked Sep 13, 2019 in Operating System by aditi19 (53 points) | 60 views

+1 vote

3 answers

http://www.cs.utexas.edu/~lorenzo/corsi/cs372/06F/hw/3sol.html

asked Sep 9, 2019 in Operating System by chirudeepnamini (13 points) | 187 views

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