Recent questions tagged pipelining
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Recent questions tagged pipelining

Recent questions tagged pipelining
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0 answers 29 views
pipeline-Hazard
Our system has single memory port, but a separate port is available dedicated to the stack.Note that out instruction uses an I/O port isolated from the memory. We need to find the type of hazards possible in the following . SOLUTION: Instruction 2, 3 has data ... dependency hazard because of bx I came up with this answer, please can you guide me if i am wrong or missed something.
Autumn asked in CO & Architecture Sep 1
by Autumn
71 points
29 views
0 votes
0 answers 30 views
Pipeline-hazard
Question: Consider the code sequence shown below running on the basic 5-stage instruction pipeline. Each stage takes 1 cycle without hazards. The pipeline stalls on data dependencies that cannot be fully resolved by forwarding. Load instructions do not have delay slots ... of cycle it take to complete ANSWER: Can you please guide me with the below solution, where it goes wrong.
Autumn asked in CO & Architecture Sep 1
by Autumn
71 points
30 views
0 votes
0 answers 25 views
geeks for geeks quiz
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown : What is the number of cycles needed to execute the following loop? for (i = 1; i < = 1000; i++) {I1, I2, I3, I4}
swami_9 asked in CO & Architecture Jul 22
by swami_9
5 points
25 views
0 votes
0 answers 39 views
self doubt RAW dependency Computer organanization
meivinay asked in CO & Architecture Feb 6
by meivinay
5 points
39 views
1 vote
0 answers 71 views
MADE EASY - Videos
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions S1 S2 S3 S4 I1 2 1 3 1 I2 1 1 1 3 I3 1 3 2 1 I4 3 1 1 2 What is the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} I am getting answer (20 cycles ) but they gave the answer (23 cycles)
sauravsingh243 asked in CO & Architecture Jan 29
by sauravsingh243
13 points
71 views
1 vote
0 answers 37 views
No source. Made up the question from PYQ
A pipeline with 4 stages :- IF, ID, EX, WB. IF, ID, WB all take 1 cycle each. EX takes 1 cycle for ADD, 1 for SUB, 3 for MUL. Pipeline cycle time is 3 ns. Out of 1000 instructions, 300 are for ADD, 500 are for SUB and 200 are for MUL. Calculate pipeline efficiency Can someone please explain me its solution?
ritik8699 asked in CO & Architecture Jan 22
by ritik8699
9 points
37 views
0 votes
0 answers 32 views
Made Easy Mock
A 5 stage pipelined processor has the following stages: IF : Instruction fetch, ID : Instruction decode, EX : Execute, MA : Memory access, WB : Write back Number of cycles, using operand forwarding ?
anurags228 asked in CO & Architecture Jan 18
by anurags228
23 points
32 views
0 votes
0 answers 13 views
Applied Gate Grand Test
Consider the following fragment of MIPS code: sw r16,12(r6) lw r16,8(r6) beq r5,r4,Label # Assume r5!=r4 add r5,r1,r4 slt r5,r15,r4 What are the total number of cycles for this instruction sequence in the 5-stage(IF, ID, EX, MEM, WB) pipeline that only has one memory.
anurags228 asked in CO & Architecture Jan 7
by anurags228
23 points
13 views
0 votes
0 answers 17 views
Gre pipelinimg
Plz post thr solution
Amit puri asked in CO & Architecture Dec 29, 2020
by Amit puri
5 points
17 views
0 votes
0 answers 22 views
GeeksforGeeks
Consider a RISC pipeline having 5 stages (instruction fetch, decode, Execute, Memory, Write back), Find how many cycles are required for the instruction given below, assume operand forwarding, branch prediction is used in which the branch is not taken and BEQ is the branch instruction. I1: BEQ R0, R1,X ... I4: X: ADD R5, R1, R2 I5: LOAD R1, 0(R5) I6: SUB R1, R1, R4 I7: ADD R1, R1, R5
AMANGOEL007 asked in CO & Architecture Dec 22, 2020
by AMANGOEL007
5 points
22 views
0 votes
0 answers 21 views
Ace test Series
Hi, Should not we solve it like..instructions from 1-15 = (k+n-1) = 5 + 14 = 19, assuming branch takes at exe stage so 3 stall cycle then instructions from 75-100 will take 26 clock cycles.. I feel the question is incorrect. Please help me with this doubt..
vipin.gautam1906 asked in CO & Architecture Dec 8, 2020
by vipin.gautam1906
9 points
21 views
0 votes
0 answers 41 views
MadeEasy-TESTseries
I am getting 1.15 as a answer? is the given answer to this correct?
Sinchit asked in CO & Architecture Nov 30, 2020
by Sinchit
17 points
41 views
0 votes
0 answers 73 views
Made Easy Book Computer organization and architecture
HAWAKASANA asked in CO & Architecture Nov 20, 2020
by HAWAKASANA
5 points
73 views
0 votes
0 answers 84 views
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Love Barot asked in CO & Architecture Oct 23, 2020
by Love Barot
7 points
84 views
0 votes
0 answers 34 views
Self doubt on number of data dependencies
What is the answer for this question - https://gateoverflow.in/29896/number-of-war-dependencies 9 or 11?
nvs16 asked in CO & Architecture Sep 20, 2020
by nvs16
9 points
34 views
0 votes
0 answers 39 views
Self Doubt on pipelining and flow dependency
Does true/flow dependency always produce one or more stalls in the pipeline?
nvs16 asked in CO & Architecture Sep 20, 2020
by nvs16
9 points
39 views
0 votes
0 answers 53 views
Carl Hamacher
What is the meaning of Branch folding in pipelining?
nvs16 asked in CO & Architecture Sep 7, 2020
by nvs16
9 points
53 views
0 votes
0 answers 78 views
COA MADE EASY TEST SERIES pipelining question
A system employs 8 stage instruction pipeline in which 1-% instructions results in data dependency, 10% instructions results in control dependency and 5% instructions results in structural dependency. 10% instructions are exposed to data and control dependencies. If ... dependency. What is the average instruction time? a)1.1 cc b)1.4cc 3)1.3cc 4)1.5cc
ijnuhb asked in CO & Architecture Sep 1, 2020
by ijnuhb
751 points
78 views
0 votes
0 answers 23 views
GOF, Made Easy
In this question Arjun sir has used operand forwarding from EX in I3 to EX in I4. Instead, can we think of it like split phase between EX in I3 to ID in I4? https://gateoverflow.in/34735/madeeasy-test-series-co-%26-architecture-pipelining
pranavsettaluri9 asked in CO & Architecture Jul 7, 2020
by pranavsettaluri9
5 points
23 views
0 votes
0 answers 21 views
Self doubt : Pipelining hazards
We are having a five-stage RISC architecture pipeline where the stages are instruction fetch ->decode->execute->memory access->write back, in which we are executing a single instruction ADD R1,R2,R3. As we can see that this ... a memory access stage then the total number of cycles required to execute this single instruction is 4 cycles or 5 cycles?
bittujash asked in CO & Architecture Jul 1, 2020
by bittujash
5 points
21 views
0 votes
0 answers 21 views
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tanmoy asked in CO & Architecture Jun 15, 2020
by tanmoy
7 points
21 views
0 votes
0 answers 18 views
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tanmoy asked in CO & Architecture Jun 14, 2020
by tanmoy
7 points
18 views
0 votes
0 answers 41 views
computer organization(architecture) question
A computer system has 64KB main memory and 1KB data cache memory. Data transfer between cache and main memory is done using 16 * 8 blocks. The set associative method, which includes 2 blocks in each set (set), is used. LRU (Least ... in the first accesses. During the running of the program, you can show and transfer data between main memory and cache.
helixum asked in CO & Architecture Jun 12, 2020
by helixum
5 points
41 views
0 votes
0 answers 72 views
THE GATEBOOK TEST SERIES
Find the number of data dependencies in the following My doubt here is that while considering the data dependencies do we consider dependencies only in the consecutive instructions or all the instruction. I solved a question from Madeeasy workbook. where they had mentioned we only consider the dependencies from the consecutive instructions only. So I’m a confused...
ummokkate asked in CO & Architecture Jun 1, 2020
by ummokkate
33 points
72 views
0 votes
0 answers 35 views
GATE2005-68 Video Solution
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
admin asked in CO & Architecture Apr 18, 2020
by admin
581 points
35 views
0 votes
0 answers 49 views
GATE2013-45 Video Solution
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$
admin asked in CO & Architecture Apr 18, 2020
by admin
581 points
49 views
0 votes
0 answers 24 views
GATE2015-3-51 Video Solution
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$. $\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline & \text{1}& \text{2} & \text{$3$} & \text{$4$} & \text{$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______
admin asked in CO & Architecture Apr 18, 2020
by admin
581 points
24 views
0 votes
0 answers 18 views
GATE2009-28 Video Solution
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below: $\begin{array}{|c|c|c|c|c|} \hline \textbf{} & \textbf {$S _1$} &\textbf {$ ... number of cycles needed to execute the following loop? For $(i=1$ to $2)$ {I1; I2; I3; I4;} $16$ $23$ $28$ $30$
admin asked in CO & Architecture Apr 18, 2020
by admin
581 points
18 views
0 votes
0 answers 20 views
GATE2015-1-38 Video Solution
Consider a non-pipelined processor with a clock rate of $2.5$ $GHz$ and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock ... $2$ $GHz$. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.
admin asked in CO & Architecture Apr 18, 2020
by admin
581 points
20 views
0 votes
0 answers 19 views
GATE2015-2-44 Video Solution
Consider the sequence of machine instruction given below: ... operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instruction is _________.
admin asked in CO & Architecture Apr 18, 2020
by admin
581 points
19 views
0 votes
0 answers 21 views
GATE2016-1-32 Video Solution
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.
admin asked in CO & Architecture Apr 18, 2020
by admin
581 points
21 views
0 votes
0 answers 10 views
GATE2010-33 Video Solution
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ADD ... $13$ $15$ $17$ $19$
admin asked in CO & Architecture Apr 18, 2020
by admin
581 points
10 views
0 votes
0 answers 20 views
GATE2008-36 Video Solution
Which of the following are NOT true in a pipelined processor? Bypassing can handle all RAW hazards Register renaming can eliminate all register carried WAR hazards Control hazard penalties can be eliminated by dynamic branch prediction I and II only I and III only II and III only I, II and III
admin asked in CO & Architecture Apr 18, 2020
by admin
581 points
20 views
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