Recent questions tagged pipelining - GATE CSE Doubts

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self doubt RAW dependency Computer organanization

asked Feb 6 in CO & Architecture by meivinay (5 points) | 23 views

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MADE EASY - Videos
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions S1 S2 S3 S4 I1 2 1 3 1 I2 1 1 1 3 I3 1 3 2 1 I4 3 1 1 2 What is the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} I am getting answer (20 cycles ) but they gave the answer (23 cycles)

asked Jan 29 in CO & Architecture by sauravsingh243 (13 points) | 37 views

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No source. Made up the question from PYQ
A pipeline with 4 stages :- IF, ID, EX, WB. IF, ID, WB all take 1 cycle each. EX takes 1 cycle for ADD, 1 for SUB, 3 for MUL. Pipeline cycle time is 3 ns. Out of 1000 instructions, 300 are for ADD, 500 are for SUB and 200 are for MUL. Calculate pipeline efficiency Can someone please explain me its solution?

asked Jan 22 in CO & Architecture by ritik8699 (9 points) | 14 views

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Made Easy Mock
A 5 stage pipelined processor has the following stages: IF : Instruction fetch, ID : Instruction decode, EX : Execute, MA : Memory access, WB : Write back Number of cycles, using operand forwarding ?

asked Jan 18 in CO & Architecture by anurags228 (23 points) | 19 views

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Applied Gate Grand Test
Consider the following fragment of MIPS code: sw r16,12(r6) lw r16,8(r6) beq r5,r4,Label # Assume r5!=r4 add r5,r1,r4 slt r5,r15,r4 What are the total number of cycles for this instruction sequence in the 5-stage(IF, ID, EX, MEM, WB) pipeline that only has one memory.

asked Jan 7 in CO & Architecture by anurags228 (23 points) | 9 views

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Gre pipelinimg
Plz post thr solution

asked Dec 29, 2020 in CO & Architecture by Amit puri (5 points) | 9 views

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GeeksforGeeks
Consider a RISC pipeline having 5 stages (instruction fetch, decode, Execute, Memory, Write back), Find how many cycles are required for the instruction given below, assume operand forwarding, branch prediction is used in which the branch is not taken and BEQ is the branch instruction. I1: BEQ R0, R1,X ... I4: X: ADD R5, R1, R2 I5: LOAD R1, 0(R5) I6: SUB R1, R1, R4 I7: ADD R1, R1, R5

asked Dec 22, 2020 in CO & Architecture by AMANGOEL007 (5 points) | 7 views

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Made Easy Test Series
Consider a pipeline X consists of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 6ns, 4ns, 3ns, 7ns and 2ns. The alternative pipeline Y contains the same number of stages but EX stage is divided into 3 sub stages (EX1, ... which are memory based instructions then the speed up ratio of X to speed up ratio of Y is ? (Answer upto 2 decimal places)

asked Dec 21, 2020 in CO & Architecture by Rishav Chetan (9 points) | 22 views

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Ace test Series
Hi, Should not we solve it like..instructions from 1-15 = (k+n-1) = 5 + 14 = 19, assuming branch takes at exe stage so 3 stall cycle then instructions from 75-100 will take 26 clock cycles.. I feel the question is incorrect. Please help me with this doubt..

asked Dec 8, 2020 in CO & Architecture by vipin.gautam1906 (9 points) | 13 views

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MadeEasy-TESTseries
I am getting 1.15 as a answer? is the given answer to this correct?

asked Nov 30, 2020 in CO & Architecture by Sinchit (17 points) | 20 views

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Made Easy Book Computer organization and architecture

asked Nov 20, 2020 in CO & Architecture by HAWAKASANA (5 points) | 33 views

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General doubt
What do the MEM & WB stages of a 5 stage RISC processor pipeline do ?

asked Nov 2, 2020 in CO & Architecture by Ankit Raina 7 (9 points) | 17 views

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telegram internet

asked Oct 23, 2020 in CO & Architecture by Love Barot (7 points) | 44 views

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Applied CO topic wise test
A 5 staged pipelined processor has the stages , Instruction fetch(IF) , Instruction Decode(ID) , Execute(EX) ,Memory(MA) , and Write back(WB) . The number of clock cycles needed to execute the following sequence of instructions is - (Assume that no operand ... R1, R1, R4 In this question, test Series answer is given 14, but I am getting 17 cycles, Can anybody verify it.

asked Oct 5, 2020 in CO & Architecture by Ankita87077 (11 points) | 45 views

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Self doubt on number of data dependencies
What is the answer for this question - https://gateoverflow.in/29896/number-of-war-dependencies 9 or 11?

asked Sep 20, 2020 in CO & Architecture by nvs16 (9 points) | 14 views

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Self Doubt on pipelining and flow dependency
Does true/flow dependency always produce one or more stalls in the pipeline?

asked Sep 20, 2020 in CO & Architecture by nvs16 (9 points) | 11 views

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Carl Hamacher
What is the meaning of Branch folding in pipelining?

asked Sep 7, 2020 in CO & Architecture by nvs16 (9 points) | 19 views

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Carl Hamacher Pipeliniing
I am not able to understand this particular line. As to how it will work.: conversely if there is an delay in fetching instructions because of a branch or a cache miss the dispatch unit continues to issue instructions from the instruction queue It is ... chapter. Link. If anyone could explain it using a timeline diagram it would be great. I am not able to visualize it.

asked Sep 7, 2020 in CO & Architecture by nvs16 (9 points) | 43 views

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COA MADE EASY TEST SERIES pipelining question
A system employs 8 stage instruction pipeline in which 1-% instructions results in data dependency, 10% instructions results in control dependency and 5% instructions results in structural dependency. 10% instructions are exposed to data and control dependencies. If ... dependency. What is the average instruction time? a)1.1 cc b)1.4cc 3)1.3cc 4)1.5cc

asked Sep 1, 2020 in CO & Architecture by ijnuhb (741 points) | 56 views

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Self Doubt - Py (CO & Architecture)
Source : https://gateoverflow.in/1063/gate2004-69 In this question we have gate delays, latch delays and 1000 inst. and arjun sir's answer make it very clear on how to proceed without making use of any formula. Source : https://gateoverflow.in/ ... the same logic as above question I am getting answer as 164 instead of directly multiplying 15*11. Why is that $?$

asked Aug 5, 2020 in CO & Architecture by KUSHAGRA गुप्ता (1.4k points) | 25 views

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GOF, Made Easy
In this question Arjun sir has used operand forwarding from EX in I3 to EX in I4. Instead, can we think of it like split phase between EX in I3 to ID in I4? https://gateoverflow.in/34735/madeeasy-test-series-co-%26-architecture-pipelining

asked Jul 7, 2020 in CO & Architecture by pranavsettaluri9 (5 points) | 13 views

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Self doubt : Pipelining hazards
We are having a five-stage RISC architecture pipeline where the stages are instruction fetch ->decode->execute->memory access->write back, in which we are executing a single instruction ADD R1,R2,R3. As we can see that this ... a memory access stage then the total number of cycles required to execute this single instruction is 4 cycles or 5 cycles?

asked Jul 1, 2020 in CO & Architecture by bittujash (5 points) | 13 views

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isi 2004 pcb c11

asked Jun 15, 2020 in CO & Architecture by tanmoy (7 points) | 13 views

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asked Jun 14, 2020 in CO & Architecture by tanmoy (7 points) | 13 views

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computer organization(architecture) question
A computer system has 64KB main memory and 1KB data cache memory. Data transfer between cache and main memory is done using 16 * 8 blocks. The set associative method, which includes 2 blocks in each set (set), is used. LRU (Least ... in the first accesses. During the running of the program, you can show and transfer data between main memory and cache.

asked Jun 12, 2020 in CO & Architecture by helixum (5 points) | 27 views

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THE GATEBOOK TEST SERIES
Find the number of data dependencies in the following My doubt here is that while considering the data dependencies do we consider dependencies only in the consecutive instructions or all the instruction. I solved a question from Madeeasy workbook. where they had mentioned we only consider the dependencies from the consecutive instructions only. So I’m a confused...

asked Jun 1, 2020 in CO & Architecture by ummokkate (33 points) | 54 views

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GATE2005-68 Video Solution
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 23 views

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GATE2013-45 Video Solution
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 38 views

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GATE2015-3-51 Video Solution
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$. $\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline & \text{1}& \text{2} & \text{$3$} & \text{$4$} & \text{$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 16 views

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GATE2009-28 Video Solution
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below: $\begin{array}{|c|c|c|c|c|} \hline \textbf{} & \textbf {$S _1$} &\textbf {$ ... number of cycles needed to execute the following loop? For $(i=1$ to $2)$ {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 10 views

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GATE2015-1-38 Video Solution
Consider a non-pipelined processor with a clock rate of $2.5$ $GHz$ and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock ... $2$ $GHz$. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 10 views

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GATE2015-2-44 Video Solution
Consider the sequence of machine instruction given below: ... operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instruction is _________.

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 12 views

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GATE2016-1-32 Video Solution
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 13 views

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GATE2010-33 Video Solution
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ADD ... $13$ $15$ $17$ $19$

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 6 views

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GATE2008-36 Video Solution
Which of the following are NOT true in a pipelined processor? Bypassing can handle all RAW hazards Register renaming can eliminate all register carried WAR hazards Control hazard penalties can be eliminated by dynamic branch prediction I and II only I and III only II and III only I, II and III

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 13 views

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GATE2014-3-43 Video Solution
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies $1$ ns, $2.2 $ ns, $2$ ns, $1$ ... this program on the old and the new design are $P$ and $Q$ nanoseconds, respectively. The value of $P/Q$ is __________.

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 8 views

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GATE2018-50 Video Solution
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch $(IF)$, Instruction Decode $(ID)$, Operand Fetch $(OF)$, Perform Operation $(PO)$ and Writeback $(WB)$, The $IF$, $ID$, $OF$ and $WB$ ... no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instruction is _____.

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 11 views

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GATE2006-42 Video Solution
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new ... is: $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 13 views

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GATE2016-2-33 Video Solution
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3$. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________ $\text{GHz}$, ignoring delays in the pipeline registers.

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 11 views

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GATE2008-76 Video Solution
Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false, The instruction following the conditional branch instruction in memory is ... The first instruction in the taken path is executed The branch takes longer to execute than any other instruction

asked Apr 18, 2020 in CO & Architecture by admin (573 points) | 7 views

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