Recent questions tagged pipelining - GATE CSE Doubts

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MadeEasy-TESTseries
I am getting 1.15 as a answer? is the given answer to this correct?

asked 3 days ago in CO & Architecture by Sinchit (17 points) | 15 views

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Made Easy Book Computer organization and architecture

asked Nov 20 in CO & Architecture by HAWAKASANA (5 points) | 24 views

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General doubt
What do the MEM & WB stages of a 5 stage RISC processor pipeline do ?

asked Nov 2 in CO & Architecture by Ankit Raina 7 (5 points) | 14 views

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telegram internet

asked Oct 23 in CO & Architecture by Love Barot (7 points) | 25 views

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Applied CO topic wise test
A 5 staged pipelined processor has the stages , Instruction fetch(IF) , Instruction Decode(ID) , Execute(EX) ,Memory(MA) , and Write back(WB) . The number of clock cycles needed to execute the following sequence of instructions is - (Assume that no operand ... R1, R1, R4 In this question, test Series answer is given 14, but I am getting 17 cycles, Can anybody verify it.

asked Oct 5 in CO & Architecture by Ankita87077 (9 points) | 39 views

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Self doubt on number of data dependencies
What is the answer for this question - https://gateoverflow.in/29896/number-of-war-dependencies 9 or 11?

asked Sep 20 in CO & Architecture by nvs16 (9 points) | 12 views

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Self Doubt on pipelining and flow dependency
Does true/flow dependency always produce one or more stalls in the pipeline?

asked Sep 20 in CO & Architecture by nvs16 (9 points) | 10 views

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Carl Hamacher
What is the meaning of Branch folding in pipelining?

asked Sep 7 in CO & Architecture by nvs16 (9 points) | 16 views

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Carl Hamacher Pipeliniing
I am not able to understand this particular line. As to how it will work.: conversely if there is an delay in fetching instructions because of a branch or a cache miss the dispatch unit continues to issue instructions from the instruction queue It is ... chapter. Link. If anyone could explain it using a timeline diagram it would be great. I am not able to visualize it.

asked Sep 7 in CO & Architecture by nvs16 (9 points) | 36 views

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COA MADE EASY TEST SERIES pipelining question
A system employs 8 stage instruction pipeline in which 1-% instructions results in data dependency, 10% instructions results in control dependency and 5% instructions results in structural dependency. 10% instructions are exposed to data and control dependencies. If ... dependency. What is the average instruction time? a)1.1 cc b)1.4cc 3)1.3cc 4)1.5cc

asked Sep 1 in CO & Architecture by Shashank Rustagi (721 points) | 48 views

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Self Doubt - Py (CO & Architecture)
Source : https://gateoverflow.in/1063/gate2004-69 In this question we have gate delays, latch delays and 1000 inst. and arjun sir's answer make it very clear on how to proceed without making use of any formula. Source : https://gateoverflow.in/ ... the same logic as above question I am getting answer as 164 instead of directly multiplying 15*11. Why is that $?$

asked Aug 5 in CO & Architecture by KUSHAGRA गुप्ता (1.4k points) | 21 views

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GOF, Made Easy
In this question Arjun sir has used operand forwarding from EX in I3 to EX in I4. Instead, can we think of it like split phase between EX in I3 to ID in I4? https://gateoverflow.in/34735/madeeasy-test-series-co-%26-architecture-pipelining

asked Jul 7 in CO & Architecture by pranavsettaluri9 (5 points) | 11 views

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Self doubt : Pipelining hazards
We are having a five-stage RISC architecture pipeline where the stages are instruction fetch ->decode->execute->memory access->write back, in which we are executing a single instruction ADD R1,R2,R3. As we can see that this ... a memory access stage then the total number of cycles required to execute this single instruction is 4 cycles or 5 cycles?

asked Jul 1 in CO & Architecture by bittujash (5 points) | 11 views

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isi 2004 pcb c11

asked Jun 15 in CO & Architecture by tanmoy (7 points) | 11 views

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asked Jun 14 in CO & Architecture by tanmoy (7 points) | 11 views

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computer organization(architecture) question
A computer system has 64KB main memory and 1KB data cache memory. Data transfer between cache and main memory is done using 16 * 8 blocks. The set associative method, which includes 2 blocks in each set (set), is used. LRU (Least ... in the first accesses. During the running of the program, you can show and transfer data between main memory and cache.

asked Jun 12 in CO & Architecture by helixum (5 points) | 21 views

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THE GATEBOOK TEST SERIES
Find the number of data dependencies in the following My doubt here is that while considering the data dependencies do we consider dependencies only in the consecutive instructions or all the instruction. I solved a question from Madeeasy workbook. where they had mentioned we only consider the dependencies from the consecutive instructions only. So I’m a confused...

asked Jun 1 in CO & Architecture by ummokkate (39 points) | 47 views

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GATE2005-68 Video Solution
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$

asked Apr 18 in CO & Architecture by admin (197 points) | 20 views

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GATE2013-45 Video Solution
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are ... during the execution of this program, the time (in ns) needed to complete the program is $132$ $165$ $176$ $328$

asked Apr 18 in CO & Architecture by admin (197 points) | 29 views

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GATE2015-3-51 Video Solution
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$. $\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline & \text{1}& \text{2} & \text{$3$} & \text{$4$} & \text{$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______

asked Apr 18 in CO & Architecture by admin (197 points) | 10 views

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GATE2009-28 Video Solution
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below: $\begin{array}{|c|c|c|c|c|} \hline \textbf{} & \textbf {$S _1$} &\textbf {$ ... number of cycles needed to execute the following loop? For $(i=1$ to $2)$ {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

asked Apr 18 in CO & Architecture by admin (197 points) | 8 views

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GATE2015-1-38 Video Solution
Consider a non-pipelined processor with a clock rate of $2.5$ $GHz$ and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock ... $2$ $GHz$. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.

asked Apr 18 in CO & Architecture by admin (197 points) | 6 views

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GATE2015-2-44 Video Solution
Consider the sequence of machine instruction given below: ... operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instruction is _________.

asked Apr 18 in CO & Architecture by admin (197 points) | 7 views

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GATE2016-1-32 Video Solution
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.

asked Apr 18 in CO & Architecture by admin (197 points) | 9 views

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GATE2010-33 Video Solution
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ADD ... $13$ $15$ $17$ $19$

asked Apr 18 in CO & Architecture by admin (197 points) | 6 views

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GATE2008-36 Video Solution
Which of the following are NOT true in a pipelined processor? Bypassing can handle all RAW hazards Register renaming can eliminate all register carried WAR hazards Control hazard penalties can be eliminated by dynamic branch prediction I and II only I and III only II and III only I, II and III

asked Apr 18 in CO & Architecture by admin (197 points) | 9 views

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GATE2014-3-43 Video Solution
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies $1$ ns, $2.2 $ ns, $2$ ns, $1$ ... this program on the old and the new design are $P$ and $Q$ nanoseconds, respectively. The value of $P/Q$ is __________.

asked Apr 18 in CO & Architecture by admin (197 points) | 5 views

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GATE2018-50 Video Solution
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch $(IF)$, Instruction Decode $(ID)$, Operand Fetch $(OF)$, Perform Operation $(PO)$ and Writeback $(WB)$, The $IF$, $ID$, $OF$ and $WB$ ... no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instruction is _____.

asked Apr 18 in CO & Architecture by admin (197 points) | 5 views

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GATE2006-42 Video Solution
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new ... is: $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$

asked Apr 18 in CO & Architecture by admin (197 points) | 9 views

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GATE2016-2-33 Video Solution
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3$. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________ $\text{GHz}$, ignoring delays in the pipeline registers.

asked Apr 18 in CO & Architecture by admin (197 points) | 7 views

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GATE2008-76 Video Solution
Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false, The instruction following the conditional branch instruction in memory is ... The first instruction in the taken path is executed The branch takes longer to execute than any other instruction

asked Apr 18 in CO & Architecture by admin (197 points) | 5 views

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GATE2017-1-50 Video Solution
Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) ... The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is _________ .

asked Apr 18 in CO & Architecture by admin (197 points) | 5 views

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GATE2014-1-43 Video Solution
Consider a $6$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this $6$-stage pipeline, the speedup achieved with respect to non-pipelined execution if $25$% of the instructions incur $2$ pipeline stall cycles is ____________

asked Apr 18 in CO & Architecture by admin (197 points) | 3 views

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GATE2006-IT-79 Video Solution
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the ... is used. The number of clock cycles required to complete the sequence of instructions is $10$ $12$ $14$ $16$

asked Apr 18 in CO & Architecture by admin (197 points) | 8 views

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GATE2007-37, ISRO2009-37 Video Solution
Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage ... $ R5$-$R4} \\ \end{array}$ $7$ $8$ $10$ $14$

asked Apr 18 in CO & Architecture by admin (197 points) | 5 views

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GATE2000-12 Video Solution
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction is ... 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.

asked Apr 18 in CO & Architecture by admin (197 points) | 4 views

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GATE2012-20, ISRO2016-23 Video Solution
Register renaming is done in pipelined processors: as an alternative to register allocation at compile time for efficient access to function parameters and local variables to handle certain kinds of hazards as part of address translation

asked Apr 18 in CO & Architecture by admin (197 points) | 8 views

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GATE2015-3-47 Video Solution
Consider the following code sequence having five instructions from $I_1 \text{ to } I_5$. Each of these instructions has the following format. OP Ri, Rj, Rk Where operation OP is performed on contents of registers Rj and Rk and the result is stored in register ... statements is/are correct? Only S1 is true Only S2 is true Only S1 and S3 are true Only S2 and S3 are true

asked Apr 18 in CO & Architecture by admin (197 points) | 17 views

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GATE2004-69 Video Solution
A 4-stage pipeline has the stage delays as $150$, $120$, $160$ and $140$ $nanoseconds$, respectively. Registers that are used between the stages have a delay of $5$ $nanoseconds$ ... be: $\text{120.4 microseconds}$ $\text{160.5 microseconds}$ $\text{165.5 microseconds}$ $\text{590.0 microseconds}$

asked Apr 18 in CO & Architecture by admin (197 points) | 4 views

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GATE2007-IT-6, ISRO2011-25 Video Solution
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed? $1.83$ $2$ $3$ $6$

asked Apr 18 in CO & Architecture by admin (197 points) | 4 views

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