# Recent questions tagged virtual-memory

I have been studying the virtual memory concept in Operating Systems. I understand that : Each process is given its own virtual address space - which might be very larger than the physical address space - to execute. If the processes cannot accommodate its pages in the main memory, we ... with each process is $2^{64}$), but obviously my secondary memory is not $2^{64}$ bytes. What am I missing?
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and cache access are sequential. Access to main memory ... Compute the average memory access latencies when the cache is physically addresses (in cycles). A) 2.45 B) 9.35 C) 15.75 D) 18.25
Calculate the overhead due to page table if given the average process in bytes is 16-bytes, the page size is 32-bytes and the page entry is 2-bytes. 15 17 18 19
In this pqy : https://gateoverflow.in/916/gate2003-26, the selected answer says that there is no external fragmentation. Since it is only 1 level paging and the page table size after calculation is greater than page size, so it can't be fit into 1 ... than page size and thus causes external fragmentation. So, shouldn't the translation not be possible because of external frag at first place.
Consider a movie player application that supports functions like play movie, skip forward x frames and skip backward x frames. Suggest a memory management policy that will be best suited for this application. (source: question 4.4 ) Ans is given as: A paging based system with ... once. And if we use Look-ahead as in paging, then this will perform equally well, if not better. Please comment on it.
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ ... level page tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The TLB ... average instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $10$ most ... access a virtual address is approximately (to the nearest $0.5$ ns) $1.5$ ns $2$ ns $3$ ns $4$ ns
A computer uses $46-bit$ virtual address, $32-bit$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $(T1)$, which occupies exactly one page. Each entry of $T1$ stores the base address of a page of ... cache block size is $64$ bytes. What is the size of a page in $KB$ in this computer? $2$ $4$ $8$ $16$
Consider a machine with $64$ MB physical memory and a $32$-bit virtual address space. If the page size s $4$ KB, what is the approximate size of the page table? $\text{16 MB}$ $\text{8 MB}$ $\text{2 MB}$ $\text{24 MB}$
A computer uses $46-bit$ virtual address, $32-bit$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table ($T1$), which occupies exactly one page. Each entry of $T1$ stores the base ... needed to guarantee that no two synonyms map to different sets in the processor cache of this computer? $2$ $4$ $8$ $16$
Let the page fault service time be $10$ milliseconds(ms) in a computer with average memory access time being $20$ nanoseconds (ns). If one page fault is generated every $10^6$ memory accesses, what is the effective access time for memory? $21$ ns $30$ ns $23$ ns $35$ ns
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is: $\text{11 bits}$ $\text{13 bits}$ $\text{15 bits}$ $\text{20 bits}$
A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $10$ most ... the page tables of this process is $\text{8 KB}$ $\text{12 KB}$ $\text{16 KB}$ $\text{20 KB}$
1 vote
Which of the following statements is false? Virtual memory implements the translation of a program's address space into physical memory address space Virtual memory allows each program to exceed the size of the primary memory Virtual memory increases the degree of multiprogramming Virtual memory reduces the context switching overhead
The minimum number of page frames that must be allocated to a running process in a virtual memory environment is determined by the instruction set architecture page size number of processes in memory physical memory size
A computer system supports $32$-bit virtual addresses as well as $32$-bit physical addresses. Since the virtual address space is of the same size as the physical address space, the operating system designers decide to get rid of the virtual memory entirely. ... can be made more efficient now Hardware support for memory management is no longer needed CPU scheduling can be made more efficient now
A computer system implements $8$ $\text{kilobyte}$ pages and a $32-bit$ physical address space. Each page table entry contains a valid bit, a dirty bit, three permission bits, and the translation. If the maximum size of the page table of a process is $24$ $\text{megabytes}$, the length of the virtual address supported by the system is _______ bits.
In a two-level virtual memory, the memory access time for main memory, $t_{M}=10^{-8}$ sec, and the memory access time for the secondary memory, $t_D=10^{-3}$ sec. What must be the hit ratio, $H$ such that the access efficiency is within $80$ percent of its maximum value?
A computer system implements a $40-bit$ virtual address, page size of $8$ $\text{kilobytes}$, and a $128-entry$ translation look-aside buffer ($TLB$) organized into $32$ sets each having $4$ ways. Assume that the $TLB$ tag does not store any process id. The minimum length of the $TLB$ tag in bits is ____.
Suppose the time to service a page fault is on the average $10$ milliseconds, while a memory access takes $1$ microsecond. Then a $99.99\%$ hit ratio results in average memory access time of $1.9999$ milliseconds $1$ millisecond $9.999$ microseconds $1.9999$ microseconds
The address sequence generated by tracing a particular program executing in a pure demand paging system with $100$ bytes per page is $\text{0100, 0200, 0430, 0499, 0510, 0530, 0560, 0120, 0220, 0240, 0260, 0320, 0410.}$ Suppose that the memory can store only one page and if $x$ is the ... $x$ to $\text{x + 99}$ are loaded on to the memory. How many page faults will occur? $0$ $4$ $7$ $8$
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: before effective address calculation has started during effective address calculation after effective address calculation has completed after data cache lookup has completed
If an instruction takes $i$ microseconds and a page fault takes an additional $j$ microseconds, the effective instruction time if on the average a page fault occurs every $k$ instruction is: $i + \dfrac{j}{k}$ $i +(j\times k)$ $\dfrac{i+j}{k}$ $({i+j})\times {k}$
A multi-user, multi-processing operating system cannot be implemented on hardware that does not support Address translation DMA for disk transfer At least two modes of CPU execution (privileged and non-privileged) Demand paging
A certain computer system has the segmented paging architecture for virtual memory. The memory is byte addressable. Both virtual and physical address spaces contain $2^{16}$ bytes each. The virtual address space is divided into $8$ non-overlapping equal size segments. The ... are available in page table entry for storing the aging information for the page? Assume that the page size is $512$ bytes.
Assume that in a certain computer, the virtual addresses are $64$ bits long and the physical addresses are $48$ bits long. The memory is word addressible. The page size is $8$ kB and the word size is $4$ bytes. The Translation Look-aside Buffer (TLB) in the address translation path has $128$ valid ... without any TLB miss? $16 \times 2^{10}$ $256 \times 2^{10}$ $4 \times 2^{20}$ $8 \times 2^{20}$
Consider a computer system with $40$-bit virtual addressing and page size of sixteen kilobytes. If the computer system has a one-level page table per process and each page table entry requires $48$ bits, then the size of the per-process page table is __________ megabytes.
03. Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: (iii) The total size of address space in a virtual memory system is limited by: the length of MAR the available secondary storage the available main memory all of the above none of the above
Where does the swap space reside? RAM Disk ROM On-chip cache
In a system with $\text{32 bit}$ virtual addresses and $\text{1 KB}$ page size, use of one-level page tables for virtual to physical address translation is not practical because of the large amount of internal fragmentation the large amount of external fragmentation the large memory overhead in maintaining page tables the large computation overhead in the translation process
A computer uses $32-bit$ virtual address, and $32-bit$ physical address. The physical memory is byte addressable, and the page size is $4$ $\text{kbytes}$ . It is decided to use two level page tables to translate from virtual address to physical ... entries that can be contained in each page? How many bits are available for storing protection and other information in each page table entry?
Consider a paging hardware with a $TLB$. Assume that the entire page table and all the pages are in the physical memory. It takes $10$ milliseconds to search the $TLB$ and $80$ milliseconds to access the physical memory. If the $TLB$ hit ratio is $0.6$, the effective memory access time (in milliseconds) is _________.
In a paged segmented scheme of memory management, the segment table itself must have a page table because The segment table is often too large to fit in one page Each segment is spread over a number of pages Segment tables point to page tables and not to the physical locations of the segment The processor’s description base register points to a page table
A multilevel page table is preferred in comparison to a single level page table for translating virtual address to physical address because It reduces the memory access time to read or write a memory location. It helps to reduce the size of page table needed ... process It is required by the translation lookaside buffer. It helps to reduce the number of page faults in page replacement algorithms.
A paging scheme uses a Translation Look-aside Buffer (TLB). A TLB-access takes $10$ ns and the main memory access takes $50$ ns. What is the effective access time(in ns) if the TLB hit ratio is $\text{90%}$ and there is no page-fault? $54$ $60$ $65$ $75$
Consider a process executing on an operating system that uses demand paging. The average time for a memory access in the system is $M$ units if the corresponding memory page is available in memory, and $D$ units if the memory access causes a page fault. It has been experimentally measured that the average time taken for a memory ... . $(D-M) / X-M)$ $(X-M) / D-M)$ $(D-X) / D-M)$ $(X-M) / D-X)$