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Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory is 100 cycles.The hit time of L2 cache is 20 cycle.The hit time of the L1 cache is 10 cycles. If there are 2.5 memory references per instruction.How many average stall cycles per instructions are there?
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At @manu thakur sir notes

This formula given but solution I an not getting .

If miss rate in L1 are 50/500 

Then in L2 should be 20/ 500  but in solution it is taken 20/50 how? Please some explain

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It is like 500 students appeared for an exam and each student was given 2 chance to clear the exam.

In first round, 50 student were not able to qualify so they go for round 2. i.e. 50/500 didn’t qualified

In round 2, 20 were not able to qualify the exam i.e. 20/50 didn’t qualified. here we are not writing 20/500 because only 50 students gave 2nd round.

I hope you can relate now.

https://gateoverflow.in/91103/madeeasy-test-series-co-%26-architecture-cache-memory

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Thank you
Nice explanation got it .
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please close this question if your doubt is resolved.
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