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The designers of a computer must select a cache system. They have two options.
Design #1 uses a direct-mapped cache containing 2 words per cache line. It would have an instruction miss rate of 3% and a data miss rate of 8%
Design #2 uses a 2-way set associative cache containing 8 words per cache line. It would have an instruction miss rate of 1% and a data miss rate of 4%
For each design, there will be approximately 0.5 data references on average per instruction. The cache miss penalty in clock cycles is 8 + cache line size in words; for example, the penalty with 1-word cache lines would be 8+1=9 clock cycles
Let D1 = cycles wasted by Design #1 on cache miss penalties (per instruction)
Let D2 = cycles wasted by Design #2 on cache miss penalties (per instruction)
On average, how many clock cycles will be wasted by cache on cache miss penalties?

A. D1 = 0.45, D2 = 0.48
B. D1 = 0.70, D2 = 0.40
C. D1 = 0.70, D2 = 0.48
D. D1 = 1.10, D2 = 0.40
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Is it D?
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Nope
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Is option A correct ?
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Still no :p
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Have they given percentage of clock cycles wasted in the answer ?
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"For these designs, let p equal the cache miss penalty, in clock cycles, and let   and  indicate
the instruction and data miss rates, respectively. Then the total time spent on penalties, for an average instruction, is p * (1 * + 0.5 * ), since there are about 0.5 data references per instruction. Consequently, the total penalty for D1 and D2, are 0.70 and 0.48, respectively."