The designers of a computer must select a cache system. They have two options.
Design #1 uses a direct-mapped cache containing 2 words per cache line. It would have an instruction miss rate of 3% and a data miss rate of 8%
Design #2 uses a 2-way set associative cache containing 8 words per cache line. It would have an instruction miss rate of 1% and a data miss rate of 4%
For each design, there will be approximately 0.5 data references on average per instruction. The cache miss penalty in clock cycles is 8 + cache line size in words; for example, the penalty with 1-word cache lines would be 8+1=9 clock cycles
Let D1 = cycles wasted by Design #1 on cache miss penalties (per instruction)
Let D2 = cycles wasted by Design #2 on cache miss penalties (per instruction)
On average, how many clock cycles will be wasted by cache on cache miss penalties?
A. D1 = 0.45, D2 = 0.48
B. D1 = 0.70, D2 = 0.40
C. D1 = 0.70, D2 = 0.48
D. D1 = 1.10, D2 = 0.40