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Welcome to GATE CSE Doubts, where you can ask questions and receive answers from other members of the community.

Recent questions tagged made-easy-test-series

0 votes
1 answer 21 views
COA Test Series
A byte addressable computer has a small data cache capable of holding sixteen 32 bit words. Each cache block consist of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4 way set associative LRU cache is used is ________. (Upto 1 decimal places) 100, 104, 108, 104, 107, 108, 105, 102, 108, 103
A byte addressable computer has a small data cache capable of holding sixteen 32 bit words. Each cache block consist of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4 way set associative LRU cache is used is ________. (Upto 1 decimal places) 100, 104, 108, 104, 107, 108, 105, 102, 108, 103
asked Jul 18 in CO & Architecture Abhishek tarpara 13 points 21 views
0 votes
1 answer 13 views
made easy cbt
answer given is 27 how to approach these kind of questions? what forulas will be used here?
answer given is 27 how to approach these kind of questions? what forulas will be used here?
asked Jul 10 in Mathematical Logic Sharma9999999 5 points 13 views
0 votes
1 answer 13 views
#digital-logic
Suppose we are using 4-bit carry lookahead adder modules to built a 64-bit adder with a 2- level carry lookahead with ripple carry between the modules. if the delay of base gate(AND OR NOT) is 2 ns , then the worst case delay of 64 bit adder will be _______ ns?
Suppose we are using 4-bit carry lookahead adder modules to built a 64-bit adder with a 2- level carry lookahead with ripple carry between the modules. if the delay of base gate(AND OR NOT) is 2 ns , then the worst case delay of 64 bit adder will be _______ ns?
asked Jul 5 in Digital Logic Abhishek tarpara 13 points 13 views
0 votes
1 answer 21 views
#testseries #digitallogic #kmap
Which of the following statements are correct? All prime implicants are minterms but all minterms are not prime implicants(PI). If a literal is deleted from a PI then it is no longer remains an implicant. in the k-map, cube corresponding to a prime implicant may be covered by larger cube. Essential prime implicant are those which are appear in final answer.
Which of the following statements are correct? All prime implicants are minterms but all minterms are not prime implicants(PI). If a literal is deleted from a PI then it is no longer remains an implicant. in the k-map, cube corresponding to a prime implicant may be covered by larger cube. Essential prime implicant are those which are appear in final answer.
asked Jul 5 in Digital Logic Abhishek tarpara 13 points 21 views
0 votes
1 answer 22 views
#Made Easy Test Series 2022 #Algorithms-I
Assume a scenario in which min-max heap has the following property: An almost complete binary tree where each node at an even level in the tree is less than all of its descendants and each of the node at an odd level in the tree is greater than all of its ... (d) Ο(n) for max and Ο(log n) for min or Ο(n) for min and Ο(log n) for max respectively
Assume a scenario in which min-max heap has the following property: An almost complete binary tree where each node at an even level in the tree is less than all of its descendants and each of the node at an odd level in the tree is greater than all of its descendants. The worst-case ... log n) respectively (d) Ο(n) for max and Ο(log n) for min or Ο(n) for min and Ο(log n) for max respectively
asked Jun 29 in DS Sibu08 5 points 22 views
0 votes
0 answers 14 views
Made easy test series #algorithm #graph #DFS
Did not understand answer of this question plz help me to resolve problem.
Did not understand answer of this question plz help me to resolve problem.
asked Jun 26 in Algorithms taatya bichhu 5 points 14 views
0 votes
0 answers 9 views
MadeEasy TOC question
hi, this is MadeEasy TOC question. It mentions to eliminate X first and then Y. How can this be done, I mean how can we eliminate X and Y since even after subsitution they will be repeating. I know here we have to use arden’s theorem but unable to understand how to reduce. Please help…....….
hi, this is MadeEasy TOC question. It mentions to eliminate X first and then Y. How can this be done, I mean how can we eliminate X and Y since even after subsitution they will be repeating. I know here we have to use arden’s theorem but unable to understand how to reduce. Please help…....….
asked Jun 25 in Theory of Computation rish1602 9 points 9 views
0 votes
0 answers 11 views
MADE EASY TEST SERIES DBMS 2022
I cannot understand why is option D) incorrect? Can anyone give an example of how in option D) first one can contain duplicate values and second one cannot ? Kindly help me. Thanks in advance
I cannot understand why is option D) incorrect? Can anyone give an example of how in option D) first one can contain duplicate values and second one cannot ? Kindly help me. Thanks in advance
asked Jun 12 in Databases KUSHAL CHAKRABORTY 5 points 11 views
0 votes
1 answer 98 views
Made Easy COA Subject Wise
Consider a two level cache memory organization. L1 has an accessing time 30 ns and main memory access time 200 ns. Assume the hit ratio for read operation is 0.65 and 45% reference are for the write operation. The average access time for system(in ns) if it uses write through technique __________.
Consider a two level cache memory organization. L1 has an accessing time 30 ns and main memory access time 200 ns. Assume the hit ratio for read operation is 0.65 and 45% reference are for the write operation. The average access time for system(in ns) if it uses write through technique __________.
asked Sep 8, 2020 in CO & Architecture Ollie 525 points 98 views
0 votes
1 answer 97 views
Made Easy Subject Wise COA
Consider 2 MBPS I/O device interfaced to 64 bit CPU in a programmed I/O mode. Data transmission between the CPU and I/O in word wise. interrupt overhead is 3 μ sec. What is the performance gain when the device is operating under interrupt I/O over programmed I/O mode? (Please suggest some resource also to study for this topic)
Consider 2 MBPS I/O device interfaced to 64 bit CPU in a programmed I/O mode. Data transmission between the CPU and I/O in word wise. interrupt overhead is 3 μ sec. What is the performance gain when the device is operating under interrupt I/O over programmed I/O mode? (Please suggest some resource also to study for this topic)
asked Sep 8, 2020 in CO & Architecture Ollie 525 points 97 views
0 votes
1 answer 61 views
Made Easy Test Series - OS: Memory Management
I think the answer should be B). S1 is incorrect. This is because TLB needs to be saved on a context switch. TLB stores frame numbers of frequently referred pages and therefore it has to be updated on a context switch between the process. We cannot simply flush it for a process going out. Please clarify. Thanks!
I think the answer should be B). S1 is incorrect. This is because TLB needs to be saved on a context switch. TLB stores frame numbers of frequently referred pages and therefore it has to be updated on a context switch between the process. We cannot simply flush it for a process going out. Please clarify. Thanks!
asked Sep 8, 2020 in Operating System sankalpmittal 41 points 61 views
0 votes
1 answer 49 views
Made Easy Test Series - OS: Paging
I think the answer should be 22 MB. We get Page Table Entry size = (22/8) B Page table size = 2^23 * 22/8 B = 22 MB. Why have they rounded 22/8 as 3B? Answer should be 22 MB and not 24 MB. Please clarify. Thanks!
I think the answer should be 22 MB. We get Page Table Entry size = (22/8) B Page table size = 2^23 * 22/8 B = 22 MB. Why have they rounded 22/8 as 3B? Answer should be 22 MB and not 24 MB. Please clarify. Thanks!
asked Sep 8, 2020 in Operating System sankalpmittal 41 points 49 views
0 votes
0 answers 29 views
Made Easy Test Series: OS - Process Scheduling
How is the answer LIFO? If I take the following example: Process Arrival Time Burst Time Priority P0 0 3 1 P1 0 5 1 P2 3 3 1 P3 6 4 1 Now we know that the priority is dynamic and so if we draw the Gantt chart: P0 P1 P0 ... (first out) but it is the first to arrive. LIFO is clearly not being followed. Can someone clairify how the answer is LIFO? Thanks!
How is the answer LIFO? If I take the following example: Process Arrival Time Burst Time Priority P0 0 3 1 P1 0 5 1 P2 3 3 1 P3 6 4 1 Now we know that the priority is dynamic and so if we draw the Gantt chart: P0 P1 P0 P1 P0 .. 0-1 1-2 2- ... P0 has completed first (first out) but it is the first to arrive. LIFO is clearly not being followed. Can someone clairify how the answer is LIFO? Thanks!
asked Sep 7, 2020 in Operating System sankalpmittal 41 points 29 views
0 votes
1 answer 42 views
Made Easy Test Series - OS: Process Scheduling
I think the answer should be 65%. They say 8 processes arrive in 60 seconds. That means the first process will arrive at the time instant t = 7.5s. Now at the time t = 60s, 8th process will be arriving. However till this mark, 7 processes are ... 39s % of time CPU is idle = (39/60) * 100 = 65% Please clarify once if I am correct or not. Thanks!
I think the answer should be 65%. They say 8 processes arrive in 60 seconds. That means the first process will arrive at the time instant t = 7.5s. Now at the time t = 60s, 8th process will be arriving. However till this mark, 7 processes are finished. So this means, idle time = 60 - ... = 60 - 21 = 39s % of time CPU is idle = (39/60) * 100 = 65% Please clarify once if I am correct or not. Thanks!
asked Sep 6, 2020 in Operating System sankalpmittal 41 points 42 views
0 votes
1 answer 65 views
Made Easy Test Series - Operating Systems: Threads
Hello, I have following doubts: Can User Level Threads run in parallel in multiprocessor system? What problem will we be facing if we access I/O devices in user mode? Can anyone please explain? Thank you!
asked Sep 6, 2020 in Operating System sankalpmittal 41 points 65 views
1 vote
0 answers 35 views
Made easy test series
Assume that the original machine is an 8-stage pipeline with a 1 ns clock cycle. The second machine is 12 stage pipeline with 0.75 ns clock cycle. The 8-stage pipeline experiences a stall due to data hazard for every 5 instructions, ... be this time I get right solution by chance. Thankyou in advance. Reference question: https://gateoverflow.in/138662/test-series-pipelining
Assume that the original machine is an 8-stage pipeline with a 1 ns clock cycle. The second machine is 12 stage pipeline with 0.75 ns clock cycle. The 8-stage pipeline experiences a stall due to data hazard for every 5 instructions, whereas the 12 ... .may be this time I get right solution by chance. Thankyou in advance. Reference question: https://gateoverflow.in/138662/test-series-pipelining
asked Sep 6, 2020 in CO & Architecture Scion_of_fire 49 points 35 views
0 votes
1 answer 44 views
Made-easy testseries coa
Consider the type addressable memory unit of a computer has 64 K words of 16 bit each. The computer has an instruction format with 4 fields namely opcode, mode field specify 9-addressing modes, register address field with 50 registers and a memory address field. If an instruction is 32 bits long then the number of different instructions are
Consider the type addressable memory unit of a computer has 64 K words of 16 bit each. The computer has an instruction format with 4 fields namely opcode, mode field specify 9-addressing modes, register address field with 50 registers and a memory address field. If an instruction is 32 bits long then the number of different instructions are
asked Sep 6, 2020 in CO & Architecture Scion_of_fire 49 points 44 views
0 votes
1 answer 180 views
Made Easy Practice Questions
Which of the following is not involved in a memory write operation? a) MAR b) PC c) MDR d) Data bus
Which of the following is not involved in a memory write operation? a) MAR b) PC c) MDR d) Data bus
asked Sep 6, 2020 in CO & Architecture himali15 5 points 180 views
0 votes
1 answer 66 views
Made easy Workbook, Self doubt in Minimum Spanning Tree
I am having confusion in finding the value of x,y,z. How can I find the values? I can't solve any questions of this type please do explain this question in detail.
asked Sep 5, 2020 in Algorithms sarthakdarji 9 points 66 views
1 vote
1 answer 230 views
Made Easy Subject wise COA
Consider a computer system has a main memory consisting of 2M 16 bit words. It also has a 8k word cache organized in the block set associative manner, with 4 blocks per set and 32 words per block. What is the number of bits in each of the TAG, SET and word field of main memory address format?
Consider a computer system has a main memory consisting of 2M 16 bit words. It also has a 8k word cache organized in the block set associative manner, with 4 blocks per set and 32 words per block. What is the number of bits in each of the TAG, SET and word field of main memory address format?
asked Sep 5, 2020 in CO & Architecture Ollie 525 points 230 views
0 votes
0 answers 41 views
Made Easy Test Series - OS
How is the option C) satisfy bounded waiting? I mean, there can be a case where the process Q keeps on executing the while loop while process P doesn't even get the chance. Bounded waiting is the number of times/bounds after which a ... enter the critical section. The above code clearly does not support bounded wait, even with option C. Can anyone explain? Thanks!
How is the option C) satisfy bounded waiting? I mean, there can be a case where the process Q keeps on executing the while loop while process P doesn’t even get the chance. Bounded waiting is the number of times/bounds after which a process gets the chance to enter the critical section. The above code clearly does not support bounded wait, even with option C. Can anyone explain? Thanks!
asked Sep 5, 2020 in Operating System sankalpmittal 41 points 41 views
1 vote
1 answer 173 views
Made Easy Topic Wise Test Series
The question says whether the following language is CFL or not(I replaced $ with &): B = {x&w | w is a substring of x, x$\in$\Sigma ^{*}$, &$\in \Sigma$} As per my understanding, w is a substring of x, and x$\in$\Sigma ^{ ... } = {$\Sigma ^{+}$} which is regular, and therefore CFL But in the answer it was given that it is not CFL, Please someone explain.
The question says whether the following language is CFL or not(I replaced $ with &): B = {x&w | w is a substring of x, x$\in$\Sigma ^{*}$, &$\in \Sigma$} As per my understanding, w is a substring of x, and x$\in$\Sigma ^{*}$(given), $ ... $\Sigma ^{+}$} which is regular, and therefore CFL But in the answer it was given that it is not CFL, Please someone explain.
asked Sep 4, 2020 in Theory of Computation Ollie 525 points 173 views
0 votes
2 answers 56 views
Can anyone provide solution to this test series question on CN
asked Sep 3, 2020 in Computer Networks ijnuhb 747 points 56 views
0 votes
0 answers 14 views
Made easy Work book, Self doubt in Graph Based Algorithms
Which of the following is not a cross edge during given BFS traversal on G? a. d,c b. d,b c. e,b d. e,f Graph is as given below
asked Sep 3, 2020 in Algorithms sarthakdarji 9 points 14 views
0 votes
1 answer 30 views
CN ME TEST SERIES QUESTION self doubt
Consider a CSMA/CD with frame size is 20 KB and transmission rate is 10 Kbps then maximum length of the cable (km) required, if signal speed is 15 km/sec (Upto 2 decimal places) Is the answer 600?
Consider a CSMA/CD with frame size is 20 KB and transmission rate is 10 Kbps then maximum length of the cable (km) required, if signal speed is 15 km/sec (Upto 2 decimal places) Is the answer 600?
asked Sep 3, 2020 in Computer Networks ijnuhb 747 points 30 views
0 votes
1 answer 38 views
Made easy workbook, Graph Based Algorithms
Which of the following is not a cross edge during given BFS traversal on G? a) d,c b) d,b c) e,b d) e,f
Which of the following is not a cross edge during given BFS traversal on G? a) d,c b) d,b c) e,b d) e,f
asked Sep 2, 2020 in Algorithms sarthakdarji 9 points 38 views
3 votes
2 answers 328 views
COA made easy test series question on Cache memory mapping
A program is stored in a $\text{16 MB}$ main memory that is attached to a $\text{4 KB}$ direct mapped cache with a block size of $\text{16 bytes}$. The program reads 4 data words $\text{A, B, C and D}$ ... of $400$ memory references $\text{A, B, C and D}$ are located inside the cache. $\text{Which of the above statements is/are TRUE?}$
asked Sep 2, 2020 in CO & Architecture ijnuhb 747 points 328 views
0 votes
1 answer 95 views
multilevel feedback scheduling doubt
with a multilevel feedback scheduler,high priority jobs are placed at top level queue and low priority at bottom level queue is this statement True/False?
with a multilevel feedback scheduler,high priority jobs are placed at top level queue and low priority at bottom level queue is this statement True/False?
asked Sep 1, 2020 in Operating System abcd9982 87 points 95 views
0 votes
2 answers 76 views
Made Easy Topic Wise
My answer is DNS Query → HTTP GET Request → TCP SYN Given DNS Query → TCP SYN → HTTP GET Request. Am I correct?
My answer is DNS Query → HTTP GET Request → TCP SYN Given DNS Query → TCP SYN → HTTP GET Request. Am I correct?
asked Sep 1, 2020 in Computer Networks Mellophi 363 points 76 views
0 votes
0 answers 54 views
Made Easy Topic Wise
Can someone explain the process?
Can someone explain the process?
asked Sep 1, 2020 in Computer Networks Mellophi 363 points 54 views
0 votes
0 answers 37 views
cycle stealing in DMA doubt
Is this method correct
Is this method correct
asked Sep 1, 2020 in CO & Architecture ijnuhb 747 points 37 views
0 votes
0 answers 64 views
COA MADE EASY TEST SERIES pipelining question
A system employs 8 stage instruction pipeline in which 1-% instructions results in data dependency, 10% instructions results in control dependency and 5% instructions results in structural dependency. 10% instructions are exposed to data and control dependencies. If ... dependency. What is the average instruction time? a)1.1 cc b)1.4cc 3)1.3cc 4)1.5cc
A system employs 8 stage instruction pipeline in which 1-% instructions results in data dependency, 10% instructions results in control dependency and 5% instructions results in structural dependency. 10% instructions are exposed to data and control dependencies. If the penalty for structural dependency ... for data dependency. What is the average instruction time? a)1.1 cc b)1.4cc 3)1.3cc 4)1.5cc
asked Sep 1, 2020 in CO & Architecture ijnuhb 747 points 64 views
0 votes
2 answers 65 views
Made Easy Topic Wise
How are we considering the address A[15][25] for a LTM? Shouldn’t valid addresses be till i=j ?
How are we considering the address A[15][25] for a LTM? Shouldn’t valid addresses be till i=j ?
asked Aug 30, 2020 in Programming Mellophi 363 points 65 views
0 votes
1 answer 147 views
Made Easy Topic Wise
asked Aug 30, 2020 in Programming Mellophi 363 points 147 views
0 votes
1 answer 119 views
MADE EASY TEST SERIES COA
asked Aug 30, 2020 in CO & Architecture ijnuhb 747 points 119 views
0 votes
1 answer 22 views
MADE EASY TEST SERIES
asked Aug 30, 2020 in CO & Architecture ijnuhb 747 points 22 views
0 votes
1 answer 34 views
ME TEST SERIES
Can anyone tell how this works?
Can anyone tell how this works?
asked Aug 27, 2020 in Databases ijnuhb 747 points 34 views
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