A byte addressable computer has a small data cache capable of holding sixteen 32 bit words. Each cache block consist of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4 way set associative LRU cache is used is ________. (Upto 1 decimal places) 100, 104, 108, 104, 107, 108, 105, 102, 108, 103
answer given is 27 how to approach these kind of questions? what forulas will be used here?
Suppose we are using 4-bit carry lookahead adder modules to built a 64-bit adder with a 2- level carry lookahead with ripple carry between the modules. if the delay of base gate(AND OR NOT) is 2 ns , then the worst case delay of 64 bit adder will be _______ ns?
Which of the following statements are correct? All prime implicants are minterms but all minterms are not prime implicants(PI). If a literal is deleted from a PI then it is no longer remains an implicant. in the k-map, cube corresponding to a prime implicant may be covered by larger cube. Essential prime implicant are those which are appear in final answer.
Assume a scenario in which min-max heap has the following property: An almost complete binary tree where each node at an even level in the tree is less than all of its descendants and each of the node at an odd level in the tree is greater than all of its descendants. The worst-case ... log n) respectively (d) Ο(n) for max and Ο(log n) for min or Ο(n) for min and Ο(log n) for max respectively
Did not understand answer of this question plz help me to resolve problem.
hi, this is MadeEasy TOC question. It mentions to eliminate X first and then Y. How can this be done, I mean how can we eliminate X and Y since even after subsitution they will be repeating. I know here we have to use arden’s theorem but unable to understand how to reduce. Please help…....….
I cannot understand why is option D) incorrect? Can anyone give an example of how in option D) first one can contain duplicate values and second one cannot ? Kindly help me. Thanks in advance
Consider a two level cache memory organization. L1 has an accessing time 30 ns and main memory access time 200 ns. Assume the hit ratio for read operation is 0.65 and 45% reference are for the write operation. The average access time for system(in ns) if it uses write through technique __________.
Consider 2 MBPS I/O device interfaced to 64 bit CPU in a programmed I/O mode. Data transmission between the CPU and I/O in word wise. interrupt overhead is 3 μ sec. What is the performance gain when the device is operating under interrupt I/O over programmed I/O mode? (Please suggest some resource also to study for this topic)
I think the answer should be B). S1 is incorrect. This is because TLB needs to be saved on a context switch. TLB stores frame numbers of frequently referred pages and therefore it has to be updated on a context switch between the process. We cannot simply flush it for a process going out. Please clarify. Thanks!
I think the answer should be 22 MB. We get Page Table Entry size = (22/8) B Page table size = 2^23 * 22/8 B = 22 MB. Why have they rounded 22/8 as 3B? Answer should be 22 MB and not 24 MB. Please clarify. Thanks!
How is the answer LIFO? If I take the following example: Process Arrival Time Burst Time Priority P0 0 3 1 P1 0 5 1 P2 3 3 1 P3 6 4 1 Now we know that the priority is dynamic and so if we draw the Gantt chart: P0 P1 P0 P1 P0 .. 0-1 1-2 2- ... P0 has completed first (first out) but it is the first to arrive. LIFO is clearly not being followed. Can someone clairify how the answer is LIFO? Thanks!
I think the answer should be 65%. They say 8 processes arrive in 60 seconds. That means the first process will arrive at the time instant t = 7.5s. Now at the time t = 60s, 8th process will be arriving. However till this mark, 7 processes are finished. So this means, idle time = 60 - ... = 60 - 21 = 39s % of time CPU is idle = (39/60) * 100 = 65% Please clarify once if I am correct or not. Thanks!
Hello, I have following doubts: Can User Level Threads run in parallel in multiprocessor system? What problem will we be facing if we access I/O devices in user mode? Can anyone please explain? Thank you!
1 vote
Assume that the original machine is an 8-stage pipeline with a 1 ns clock cycle. The second machine is 12 stage pipeline with 0.75 ns clock cycle. The 8-stage pipeline experiences a stall due to data hazard for every 5 instructions, whereas the 12 ... .may be this time I get right solution by chance. Thankyou in advance. Reference question: https://gateoverflow.in/138662/test-series-pipelining
Consider the type addressable memory unit of a computer has 64 K words of 16 bit each. The computer has an instruction format with 4 fields namely opcode, mode field specify 9-addressing modes, register address field with 50 registers and a memory address field. If an instruction is 32 bits long then the number of different instructions are
Which of the following is not involved in a memory write operation? a) MAR b) PC c) MDR d) Data bus
I am having confusion in finding the value of x,y,z. How can I find the values? I can't solve any questions of this type please do explain this question in detail.
1 vote
Consider a computer system has a main memory consisting of 2M 16 bit words. It also has a 8k word cache organized in the block set associative manner, with 4 blocks per set and 32 words per block. What is the number of bits in each of the TAG, SET and word field of main memory address format?
How is the option C) satisfy bounded waiting? I mean, there can be a case where the process Q keeps on executing the while loop while process P doesn’t even get the chance. Bounded waiting is the number of times/bounds after which a process gets the chance to enter the critical section. The above code clearly does not support bounded wait, even with option C. Can anyone explain? Thanks!
1 vote
The question says whether the following language is CFL or not(I replaced $with &): B = {x&w | w is a substring of x, x$\in$\Sigma ^{*}$, &$\in \Sigma$} As per my understanding, w is a substring of x, and x$\in$\Sigma ^{*}$(given),$ ... $\Sigma ^{+}$} which is regular, and therefore CFL But in the answer it was given that it is not CFL, Please someone explain.
Which of the following is not a cross edge during given BFS traversal on G? a. d,c b. d,b c. e,b d. e,f Graph is as given below
Consider a CSMA/CD with frame size is 20 KB and transmission rate is 10 Kbps then maximum length of the cable (km) required, if signal speed is 15 km/sec (Upto 2 decimal places) Is the answer 600?
Which of the following is not a cross edge during given BFS traversal on G? a) d,c b) d,b c) e,b d) e,f
A program is stored in a $\text{16 MB}$ main memory that is attached to a $\text{4 KB}$ direct mapped cache with a block size of $\text{16 bytes}$. The program reads 4 data words $\text{A, B, C and D}$ ... of $400$ memory references $\text{A, B, C and D}$ are located inside the cache. $\text{Which of the above statements is/are TRUE?}$
with a multilevel feedback scheduler,high priority jobs are placed at top level queue and low priority at bottom level queue is this statement True/False?
My answer is DNS Query → HTTP GET Request → TCP SYN Given DNS Query → TCP SYN → HTTP GET Request. Am I correct?
Can someone explain the process?
Is this method correct